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  /external/u-boot/arch/arm/mach-exynos/
exynos5_setup.h 664 #define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
841 #define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
clock_init_exynos5.c 759 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
952 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);

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