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  /external/u-boot/arch/arm/mach-exynos/
exynos5_setup.h 606 #define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
793 #define CLK_DIV_TOP0_VAL 0x23712311
clock_init_exynos5.c 695 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
919 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);

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