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  /external/u-boot/arch/arm/mach-exynos/
exynos5_setup.h 628 #define CLK_DIV_TOP2_VAL NOT_AVAILABLE
795 #define CLK_DIV_TOP2_VAL 0x11101100
clock_init_exynos5.c 921 writel(CLK_DIV_TOP2_VAL, &clk->div_top2);

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