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  /external/u-boot/arch/arm/mach-exynos/
exynos5_setup.h 566 #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
785 #define CLK_SRC_TOP2_VAL 0x11101000
clock_init_exynos5.c 737 val |= CLK_SRC_TOP2_VAL;
916 writel(CLK_SRC_TOP2_VAL, &clk->src_top2);

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