| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
97 Ops[3].getAsInteger(10, CRn);
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
109 uint32_t CRn = (Bits >> 7) & 0xf;
113 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 122 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
126 Ops[3].getAsInteger(10, CRn);
129 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
138 uint32_t CRn = (Bits >> 7) & 0xf;
142 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/ |
| arch_helpers.h | 19 #define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
22 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
25 #define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
29 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
108 #define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
112 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
114 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
117 #define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
120 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
122 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/include/common/aarch32/ |
| asm_macros.S | 18 .macro ldcopr reg, coproc, opc1, CRn, CRm, opc2
19 mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2
26 .macro stcopr reg, coproc, opc1, CRn, CRm, opc2
27 mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2
|
| /device/linaro/bootloader/arm-trusted-firmware/lib/aarch32/ |
| cache_helpers.S | 22 .macro do_dcache_maintenance_by_mva op, coproc, opc1, CRn, CRm, opc2
31 stcopr r0, \coproc, \opc1, \CRn, \CRm, \opc2
|
| /external/capstone/arch/AArch64/ |
| AArch64BaseInfo.c | 633 uint32_t Op0, Op1, CRn, CRm, Op2;
670 CRn = (Bits >> 7) & 0xf;
676 if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
681 //assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
686 CRnS = utostr(CRn, false);
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ThumbDisassembler.c | 263 { "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
264 { "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
266 { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
267 { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
500 UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
[all...] |
| /external/v8/src/arm64/ |
| constants-arm64.h | 246 V_(CRn, 15, 12, Bits) \
411 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
[all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| constants-aarch64.h | 139 V_(CRn, 15, 12, ExtractBits) \
349 template<int op0, int op1, int crn, int crm, int op2>
355 (crn << CRn_offset) |
362 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
368 template<int op1, int crn, int crm, int op2>
373 (crn << CRn_offset) |
[all...] |
| assembler-aarch64.cc | [all...] |
