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  /external/llvm/lib/Target/X86/
X86MachineFunctionInfo.cpp 23 for (const MCPhysReg *CSR =
25 unsigned Reg = *CSR;
26 ++CSR)
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
X86MachineFunctionInfo.cpp 24 for (const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
25 unsigned Reg = *CSR; ++CSR) {
  /external/llvm/lib/Target/Hexagon/
HexagonGenExtract.cpp 87 ConstantInt *CSL = 0, *CSR = 0, *CM = 0;
94 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
101 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
108 CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
118 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
125 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
132 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
139 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
152 uint32_t SR = CSR->getZExtValue();
HexagonVLIWPacketizer.cpp 319 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
320 if (MI->modifiesRegister(*CSR, TRI))
    [all...]
  /external/swiftshader/third_party/LLVM/lib/CodeGen/
RegisterClassInfo.cpp 42 const unsigned *CSR = TRI->getCalleeSavedRegs(MF);
43 if (Update || CSR != CalleeSaved) {
44 // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
45 // overlapping CSR.
48 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
51 CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
54 CalleeSaved = CSR;
68 /// registers filtered out. Volatile registers come first followed by CSR
69 /// aliases ordered according to the CSR order specified by the target.
91 // PhysReg aliases a CSR, save it for later
    [all...]
MachineFunction.cpp 467 for (const unsigned *CSR = TRI->getCalleeSavedRegs(MF); CSR && *CSR; ++CSR)
468 BV.set(*CSR);
RegAllocGreedy.cpp 635 // Don't start using a CSR when the CostPerUseLimit is low.
637 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
638 if (!MRI->isPhysRegUsed(CSR)) {
639 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
640 << PrintReg(CSR, TRI) << '\n');
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
HexagonGenExtract.cpp 99 ConstantInt *CSL = nullptr, *CSR = nullptr, *CM = nullptr;
106 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
113 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
120 CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
130 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
137 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
144 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
151 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
164 uint32_t SR = CSR->getZExtValue();
HexagonVLIWPacketizer.cpp 342 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
343 if (MI.modifiesRegister(*CSR, TRI))
    [all...]
HexagonFrameLowering.cpp 121 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
283 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
313 if (CSR[*S])
323 for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
325 // If this regmask does not preserve a CSR, a frame will be needed.
436 BitVector CSR(Hexagon::NUM_TARGET_REGS);
439 CSR[*S] = true;
442 if (needsStackFrame(I, CSR, HRI))
    [all...]
  /external/llvm/lib/CodeGen/
LivePhysRegs.cpp 154 for (const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
155 LiveRegs.addReg(*CSR);
RegisterClassInfo.cpp 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
52 if (Update || CSR != CalleeSaved) {
53 // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
54 // overlapping CSR.
57 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
59 CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
62 CalleeSaved = CSR;
77 /// registers filtered out. Volatile registers come first followed by CSR
78 /// aliases ordered according to the CSR order specified by the target.
107 // PhysReg aliases a CSR, save it for later
    [all...]
MachineFunction.cpp 662 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
663 BV.set(*CSR);
    [all...]
RegAllocPBQP.cpp 554 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF);
555 for (unsigned i = 0; CSR[i] != 0; ++i)
556 if (TRI.regsOverlap(reg, CSR[i]))
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
LiveRegUnits.cpp 96 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR)
97 LiveUnits.addReg(*CSR);
RegisterClassInfo.cpp 59 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
60 if (Update || CSR != CalleeSavedRegs) {
61 // Build a CSRAlias map. Every CSR alias saves the last
62 // overlapping CSR.
64 for (const MCPhysReg *I = CSR; *I; ++I)
70 CalleeSavedRegs = CSR;
89 /// registers filtered out. Volatile registers come first followed by CSR
90 /// aliases ordered according to the CSR order specified by the target.
119 // PhysReg aliases a CSR, save it for later.
131 // CSR aliases go after the volatile registers, preserve the target's order
    [all...]
MachineFrameInfo.cpp 122 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR;
123 ++CSR)
124 BV.set(*CSR);
LivePhysRegs.cpp 180 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR)
181 LiveRegs.addReg(*CSR);
MachineRegisterInfo.cpp 615 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
616 for (const MCPhysReg *I = CSR; *I; ++I)
RegAllocPBQP.cpp 571 const MCPhysReg *CSR = MF.getRegInfo().getCalleeSavedRegs();
572 for (unsigned i = 0; CSR[i] != 0; ++i)
573 if (TRI.regsOverlap(reg, CSR[i]))
    [all...]
  /device/google/contexthub/firmware/os/platform/stm32/
pwr.c 51 volatile uint32_t CSR;
59 volatile uint32_t CSR;
157 static uint32_t pwrParseCsr(uint32_t csr)
161 if (csr & RCC_CSR_LPWRRSTF)
163 if (csr & RCC_CSR_WWDGRSTF)
165 if (csr & RCC_CSR_IWDGRSTF)
167 if (csr & RCC_CSR_SFTRSTF)
169 if (csr & RCC_CSR_PORRSTF)
171 if (csr & RCC_CSR_PINRSTF)
173 if (csr & RCC_CSR_BORRSTF
    [all...]
  /external/perfetto/src/trace_processor/
raw_table.cc 154 using CSR = protos::pbzero::ClkSetRateFtraceEvent;
156 write_value_at_index(CSR::kNameFieldNumber - 1, write_value);
158 write_value_at_index(CSR::kRateFieldNumber - 1, write_value);
  /external/llvm/include/llvm/ADT/
Triple.h 134 CSR,
  /external/swiftshader/third_party/llvm-subzero/include/llvm/ADT/
Triple.h 138 CSR,
  /external/u-boot/drivers/spi/
atmel_spi.c 101 spi_writel(as, CSR(cs), csrx);
267 writel(csrx, &reg_base->csr[cs]);

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