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Searched refs:DDR3PHY_CTRL_PHY_RESET (Results 1 -
2 of 2) sorted by null
Completed in 621 milliseconds
| /external/u-boot/arch/arm/mach-exynos/ | |
| exynos5_setup.h | 251 #define DDR3PHY_CTRL_PHY_RESET (1 << 0) |
| dmc_init_ddr3.c | 32 writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); |
Completed in 621 milliseconds
