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Searched refs:DDR3PHY_CTRL_PHY_RESET_OFF (Results 1 -
2 of 2) sorted by null
Completed in 226 milliseconds
| /external/u-boot/arch/arm/mach-exynos/ | |
| exynos5_setup.h | 252 #define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0) |
| dmc_init_ddr3.c | 31 writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl); |
Completed in 226 milliseconds
