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/external/u-boot/arch/arm/mach-exynos/ | |
exynos5_setup.h | 452 #define DPLL_CON1_VAL (NOT_AVAILABLE) 718 #define DPLL_CON1_VAL (0x0020F300) |
clock_init_exynos5.c | 854 writel(DPLL_CON1_VAL, &clk->dpll_con1); |