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    Searched refs:DQS (Results 1 - 3 of 3) sorted by null

  /external/u-boot/drivers/ddr/marvell/axp/
ddr3_hw_training.h 115 #define DQS 6
204 /* DQS */
ddr3_read_leveling.c 122 dram_info->rl_val[cs][pup][DQS] =
439 * Broadcast to all PUPs current RL delays: DQS phase,
732 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F);
793 * Broadcast to all PUPs current RL delays: DQS phase,leveling
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ddr3_write_leveling.c 104 * High freq Supplement and DQS Centralization
128 dram_info->wl_val[cs][pup][DQS] =
291 /* Check pup which DQS/DATA is error */
342 /* clock is longer than DQS */
356 DEBUG_WL_S("#### Clock is longer than DQS more than one clk cycle ####\n");
363 /* clock is align to DQS */
377 DEBUG_WL_S("#### Warning - Possible Layout Violation (DQS is longer than CLK)####\n");
428 * Read results to arrays - Results are required for DQS Centralization
527 * freq Supplement and DQS Centralization
564 dram_info->wl_val[cs][pup][DQS]
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