| /art/compiler/utils/arm64/ |
| assembler_arm64.cc | 106 static inline dwarf::Reg DWARFReg(CPURegister reg) {
124 cfi_.RelOffset(DWARFReg(dst0), offset);
131 cfi_.RelOffset(DWARFReg(dst0), offset);
132 cfi_.RelOffset(DWARFReg(dst1), offset + size);
138 cfi_.RelOffset(DWARFReg(dst0), offset);
150 cfi_.Restore(DWARFReg(dst0));
157 cfi_.Restore(DWARFReg(dst0));
158 cfi_.Restore(DWARFReg(dst1));
164 cfi_.Restore(DWARFReg(dst0));
|
| /art/compiler/optimizing/ |
| common_arm.h | 41 inline dwarf::Reg DWARFReg(vixl::aarch32::Register reg) {
45 inline dwarf::Reg DWARFReg(vixl::aarch32::SRegister reg) {
|
| code_generator_mips64.cc | [all...] |
| code_generator_x86_64.cc | [all...] |
| code_generator_x86.cc | [all...] |
| code_generator_arm_vixl.cc | 50 using helpers::DWARFReg;
[all...] |
| code_generator_mips.cc | [all...] |
| /art/compiler/utils/x86_64/ |
| jni_macro_assembler_x86_64.cc | 27 static dwarf::Reg DWARFReg(Register reg) {
30 static dwarf::Reg DWARFReg(FloatRegister reg) {
52 cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0);
69 cfi().RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset);
116 cfi().Restore(DWARFReg(spill.AsXmmRegister().AsFloatRegister()));
129 cfi().Restore(DWARFReg(spill.AsCpuRegister().AsRegister()));
|
| /art/compiler/utils/arm/ |
| jni_macro_assembler_arm_vixl.cc | 71 static dwarf::Reg DWARFReg(vixl32::Register reg) {
75 static dwarf::Reg DWARFReg(vixl32::SRegister reg) {
100 cfi().RelOffsetForMany(DWARFReg(r0), 0, core_spill_mask, kFramePointerSize);
109 cfi().RelOffsetForMany(DWARFReg(s0), 0, fp_spill_mask, kFramePointerSize);
171 cfi().RestoreMany(DWARFReg(s0), fp_spill_mask);
|
| /art/compiler/utils/x86/ |
| jni_macro_assembler_x86.cc | 36 static dwarf::Reg DWARFReg(Register reg) {
57 cfi().RelOffset(DWARFReg(spill), 0);
99 cfi().Restore(DWARFReg(spill));
|
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | [all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.cc | [all...] |
