| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstructionSelector.cpp | 128 unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
145 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
152 .addReg(DstHi)
|
| SIInstrInfo.cpp | [all...] |
| SIISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 575 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
577 HiInst.addReg(DstHi, RegState::Define);
|
| MipsSEFrameLowering.cpp | 249 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
256 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 270 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
277 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
[all...] |
| MipsSEInstrInfo.cpp | 733 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
735 HiInst.addReg(DstHi, RegState::Define);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 859 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
869 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
877 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
888 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
898 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | [all...] |
| HexagonInstrInfo.cpp | 847 unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg);
848 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstHi)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | [all...] |
