/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
ISDOpcodes.h | 688 /// EXTLOAD is used for two things: floating point extending loads and 692 EXTLOAD, [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
PTXISelLowering.cpp | 53 // (any/zero/sign) extload => load + (any/zero/sign) extend 55 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand); 59 // f32 extload => load + fextend 61 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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/external/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | 98 // There are no 64-bit extloads. These should be done as a 32-bit extload and 101 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); 120 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 121 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal); 122 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal); 123 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); 127 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand); 130 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand); 133 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand); 136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand) [all...] |
R600ISelLowering.cpp | 50 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address 61 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 62 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); 63 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); 67 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand); 71 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand); [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 69 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 73 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | 179 // There are no 64-bit extloads. These should be done as a 32-bit extload and 182 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); 201 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 202 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal); 203 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal); 204 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); 208 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand); 211 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand); 214 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand); 217 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand) [all...] |
R600ISelLowering.cpp | 72 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address 83 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 84 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); 85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); 89 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand); 93 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
WebAssemblyISelLowering.cpp | 102 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand); 145 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); 148 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeDAG.cpp | 359 // Only do this if the target has a native EXTLOAD instruction from 361 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 373 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 450 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 554 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 647 // with a "move to register" or "extload into register" instruction, then [all...] |
/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyISelLowering.cpp | 130 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); 133 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
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/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 209 // Turn FP extload into load/fextend 210 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); 211 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); 212 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); 213 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); 214 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand); 215 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); 216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); 217 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); 218 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 437 // Turn FP extload into load/fpextend 438 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); 439 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); 440 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); 441 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); 442 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand); 443 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); 444 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); 445 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); 446 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand) [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreISelLowering.cpp | 127 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 467 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
XCoreISelLowering.cpp | 124 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 461 DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr, [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 550 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR, 604 case ISD::EXTLOAD: [all...] |
LegalizeDAG.cpp | 267 // Only do this if the target has a native EXTLOAD instruction from 269 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && 283 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, 324 // with a "move to register" or "extload into register" instruction, then 688 // that these bits are zero. It is also useful for EXTLOAD, since it 696 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 705 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 730 assert(!SrcVT.isVector() && "Unsupported extload!"); 744 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16 [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | 92 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 182 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 116 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 120 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 121 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 141 setLoadExtAction(ISD::EXTLOAD, VT, Custom); 730 } else if (ExtType == ISD::EXTLOAD) { [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeDAG.cpp | 303 // Only do this if the target has a native EXTLOAD instruction from 305 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && 320 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, 359 // with a "move to register" or "extload into register" instruction, then 719 // that these bits are zero. It is also useful for EXTLOAD, since it 727 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 736 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 759 assert(!SrcVT.isVector() && "Unsupported extload!"); 773 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16 [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 256 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 415 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 318 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 326 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 327 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 334 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 491 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelDAGToDAG.cpp | 251 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); 306 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { [all...] |