| /art/compiler/utils/arm/ |
| assembler_arm_vixl.h | 88 WITH_FLAGS_DONT_CARE_RD_RN_OP(Eor);
|
| /external/v8/src/wasm/baseline/arm64/ |
| liftoff-assembler-arm64.h | 405 I32_BINOP(i32_xor, Eor)
414 I64_BINOP(i64_xor, Eor)
|
| /external/swiftshader/third_party/subzero/src/ |
| IceInstARM32.h | 392 Eor,
[all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm_vixl.cc | [all...] |
| code_generator_vector_arm64.cc | 368 __ Eor(dst.V16B(), dst.V16B(), src.V16B());
836 __ Eor(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter
[all...] |
| intrinsics_arm64.cc | [all...] |
| code_generator_arm_vixl.cc | [all...] |
| code_generator_arm64.cc | [all...] |
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | [all...] |
| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | [all...] |
| test-assembler-aarch32.cc | 686 __ eor(r5, r2, r3); // Ensure that r2, r3 and r4 are identical.
687 __ eor(r6, r2, r4);
698 __ eor(r1, r1, r2);
[all...] |
| test-simulator-cond-rd-rn-operand-rm-a32.cc | 124 M(Eor) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-t32.cc | 124 M(Eor) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-a32.cc | 124 M(Eor) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-t32.cc | 124 M(Eor) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 124 M(Eor) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 124 M(Eor) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 124 M(Eor) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 124 M(Eor) \
[all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | 385 __ Eor(x11, x0, 0x18001);
837 __ Eor(w13, w0, kWMinInt);
[all...] |
| test-disasm-aarch64.cc | 175 COMPARE(dci(0x521e0400), "eor w0, w0, #0xc");
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64.h | 398 V(eor, Eor) \
619 inline void Eor(const Register& rd, const Register& rn,
[all...] |
| macro-assembler-arm64-inl.h | 76 void TurboAssembler::Eor(const Register& rd, const Register& rn,
80 LogicalMacro(rd, rn, operand, EOR);
[all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | 657 void Eor(const Register& rd, const Register& rn, const Operand& operand);
[all...] |
