HomeSort by relevance Sort by last modified time
    Searched refs:F0 (Results 1 - 25 of 118) sorted by null

1 2 3 4 5

  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/
BoardGpios.h 45 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
46 GPIO_INIT_ITEM("PLT_CLK0 GPIOC_96 " ,TRISTS ,NA ,F0 , , ,NONE ,0x6a),
47 GPIO_INIT_ITEM("PLT_CLK3 GPIOC_99 " ,TRISTS ,NA ,F0 , , ,NONE ,0x68),
144 GPIO_INIT_ITEM("PANEL0_VDDEN GPIONC_3 " ,GPIO ,NA ,F0 , , ,NONE ,0x14),
145 GPIO_INIT_ITEM("PANEL0_BKLTEN GPIONC_4 " ,GPIO ,NA ,F0 , , ,NONE ,0x15),
146 GPIO_INIT_ITEM("PANEL0_BKLTCTL GPIONC_5 " ,GPIO ,NA ,F0 , , ,NONE ,0x16),
150 GPIO_INIT_ITEM("PANEL1_VDDEN GPIONC_9 " ,GPIO ,NA ,F0 , , ,NONE ,0x10),
151 GPIO_INIT_ITEM("PANEL1_BKLTEN GPIONC_10" ,GPIO ,NA ,F0 , , ,NONE ,0x0e),
152 GPIO_INIT_ITEM("PANEL1_BKLTCTL GPIONC_11" ,GPIO ,NA ,F0 , , ,NONE ,0x0f),
153 GPIO_INIT_ITEM("GP_INTD_DSI_TE1 GPIONC_12" ,GPO ,NA ,F0 , , ,NONE ,0x0c),
    [all...]
  /external/compiler-rt/test/asan/TestCases/Posix/
coverage-direct-large.cc 25 #define F0(Q, x) Q(x)
27 F0(Q, x##0) F0(Q, x##1) F0(Q, x##2) F0(Q, x##3) F0(Q, x##4) F0(Q, x##5) \
28 F0(Q, x##6) F0(Q, x##7) F0(Q, x##8) F0(Q, x##9
    [all...]
  /external/mksh/src/
var_spec.h 26 #define F0(name) V_##name = 0,
28 #define F0(name) /* nothing */
32 #ifndef F0
33 #define F0 FN
36 /* NOTE: F0 are skipped for the ITEMS array, only FN generate names */
39 F0(NONE)
77 #undef F0
emacsfn.h 26 #define F0(cname,sname,flags) XFUNC_##cname = 0,
31 #ifndef F0
32 #define F0 FN
35 F0(abort, "abort", 0)
110 #undef F0
sh_flags.gen 27 #define F0(sname,cname,flags,ochar) cname = 0,
31 #ifndef F0
32 #define F0 FN
34 F0("allexport", FEXPORT, OF_ANY, 'a')
100 #undef F0
exprtok.h 28 #define F0(name, len, prec, enum) enum = 0,
44 #ifndef F0
45 #define F0 FN
115 #undef F0
rlimits.gen 28 #ifndef F0
29 #define F0 FN
103 #undef F0
  /art/compiler/utils/mips/
assembler_mips32r5_test.cc 157 fp_registers_.push_back(new mips::FRegister(mips::F0));
280 __ LoadQFromOffset(mips::F0, mips::A0, 0);
281 __ LoadQFromOffset(mips::F0, mips::A0, 1);
282 __ LoadQFromOffset(mips::F0, mips::A0, 2);
283 __ LoadQFromOffset(mips::F0, mips::A0, 4);
284 __ LoadQFromOffset(mips::F0, mips::A0, 8);
285 __ LoadQFromOffset(mips::F0, mips::A0, 511);
286 __ LoadQFromOffset(mips::F0, mips::A0, 512);
287 __ LoadQFromOffset(mips::F0, mips::A0, 513);
288 __ LoadQFromOffset(mips::F0, mips::A0, 514)
    [all...]
assembler_mips32r6_test.cc 170 fp_registers_.push_back(new mips::FRegister(mips::F0));
391 (Base::GetAssembler()->*f)(mips::F0, &label, is_bare);
406 instr_name + " $f0, 1f\n" +
673 __ LoadDFromOffset(mips::F0, mips::A0, -0x8000);
674 __ LoadDFromOffset(mips::F0, mips::A0, +0);
675 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FF8);
676 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFB);
677 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFC);
678 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFF);
679 __ LoadDFromOffset(mips::F0, mips::A0, -0xFFF0)
    [all...]
  /external/llvm/unittests/ADT/
BitmaskEnumTest.cpp 17 F0 = 0,
83 EXPECT_EQ(15, ~F0);
87 F0 = 0,
95 FlagsClass f = (FlagsClass::F1 & ~FlagsClass::F0) | FlagsClass::F2;
101 enum Flags { F0 = 0, F1 = 1, F2 = 2, F3 = 4, LLVM_MARK_AS_BITMASK_ENUM(F3) };
104 Flags f = F0 | F1;
118 F0 = 0,
130 foo::bar::FlagsInNamespace f = ~foo::bar::F0 & (foo::bar::F1 | foo::bar::F2);
  /external/swiftshader/third_party/llvm-7.0/llvm/unittests/ADT/
BitmaskEnumTest.cpp 17 F0 = 0,
83 EXPECT_EQ(15, ~F0);
87 F0 = 0,
95 FlagsClass f = (FlagsClass::F1 & ~FlagsClass::F0) | FlagsClass::F2;
101 enum Flags { F0 = 0, F1 = 1, F2 = 2, F3 = 4, LLVM_MARK_AS_BITMASK_ENUM(F3) };
104 Flags f = F0 | F1;
118 F0 = 0,
130 foo::bar::FlagsInNamespace f = ~foo::bar::F0 & (foo::bar::F1 | foo::bar::F2);
  /external/clang/test/CXX/dcl.dcl/basic.namespace/namespace.def/namespace.memdef/
p3.cpp 11 friend struct F0;
12 friend void f0(int);
13 struct F0 member_func();
15 struct F0 { };
16 F0 f0() { return S0().member_func(); } function in namespace:N
18 N::F0 f0_var = N::f0();
  /device/linaro/bootloader/edk2/Nt32Pkg/Library/PeiNt32PeCoffExtraActionLib/
PeiNt32PeCoffExtraActionLib.inf 21 FILE_GUID = 057C712A-84F0-4f4a-94CB-713EEF002E2F
  /external/openssh/openbsd-compat/
rmd160.c 78 #define F0(x, y, z) ((x) ^ (y) ^ (z))
191 R(a, b, c, d, e, F0, K0, 11, 0);
192 R(e, a, b, c, d, F0, K0, 14, 1);
193 R(d, e, a, b, c, F0, K0, 15, 2);
194 R(c, d, e, a, b, F0, K0, 12, 3);
195 R(b, c, d, e, a, F0, K0, 5, 4);
196 R(a, b, c, d, e, F0, K0, 8, 5);
197 R(e, a, b, c, d, F0, K0, 7, 6);
198 R(d, e, a, b, c, F0, K0, 9, 7);
199 R(c, d, e, a, b, F0, K0, 11, 8)
    [all...]
  /device/linaro/bootloader/edk2/ArmPkg/Library/ArmExceptionLib/
ArmExceptionLib.inf 32 FILE_GUID = A9796991-4E88-47F0-87C5-D96A1D270539
  /device/linaro/bootloader/edk2/IntelFrameworkPkg/Library/PeiSmbusLibSmbusPpi/
PeiSmbusLibSmbusPpi.inf 20 FILE_GUID = 51C4C059-67F0-4e3c-9A55-FF42A8291C8C
  /external/llvm/test/MC/MachO/ARM/
relax-thumb2-branches.s 29 @ CHECK: 00F0: 00000000 00000000 00000000 00000000 |................|
45 @ CHECK: 01F0: 00000000 00000000 00000000 00000000 |................|
  /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/MachO/ARM/
relax-thumb2-branches.s 29 @ CHECK: 00F0: 00000000 00000000 00000000 00000000 |................|
45 @ CHECK: 01F0: 00000000 00000000 00000000 00000000 |................|
  /art/compiler/utils/mips64/
managed_register_mips64_test.cc 111 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0);
118 EXPECT_EQ(F0, reg.AsFpuRegister());
120 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
158 Mips64ManagedRegister freg = Mips64ManagedRegister::FromFpuRegister(F0);
165 EXPECT_EQ(F0, reg.AsOverlappingFpuRegister());
208 EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
216 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
225 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
234 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromFpuRegister(F0)));
237 Mips64ManagedRegister reg_F0 = Mips64ManagedRegister::FromFpuRegister(F0);
    [all...]
assembler_mips64_test.cc 168 fp_registers_.push_back(new mips64::FpuRegister(mips64::F0));
381 (Base::GetAssembler()->*f)(mips64::F0, &label, is_bare);
396 instr_name + " $f0, 1f\n" +
    [all...]
  /external/clang/test/SemaCXX/
rval-references-examples.cpp 95 struct F0 {
101 f(static_cast<Args&&>(args)...); // expected-error{{no matching function for call to object of type 'perfect_forwarding::F0'}}
107 forward(F0(), get<A&>(), get<A const&>(), get<A>(), get<const A>(),
109 forward(F0(), get<A&>(), get<A const&>(), get<A>(), get<const A>(), // expected-note{{in instantiation of function template specialization 'perfect_forwarding::forward<perfect_forwarding::F0, perfect_forwarding::A &, const perfect_forwarding::A &, perfect_forwarding::A, const perfect_forwarding::A, const perfect_forwarding::A, const perfect_forwarding::A>' requested here}}
  /art/runtime/arch/mips/
registers_mips.cc 40 if (rhs >= F0 && rhs < kNumberOfFRegisters) {
  /art/runtime/arch/mips64/
registers_mips64.cc 41 if (rhs >= F0 && rhs < kNumberOfFpuRegisters) {
  /external/tensorflow/tensorflow/lite/kernels/internal/reference/integer_ops/
mul.h 70 // F0 uses 0 integer bits, range [-1, 1].
71 using F0 = gemmlowp::FixedPoint<std::int16_t, 0>;
73 F0 unclamped_result =
74 F0::FromRaw(input1_data[i]) * F0::FromRaw(input2_data[i]);
  /external/clang/test/Layout/
ms-x86-basic-layout.cpp 492 struct F0 : A4, B {
494 F0() : a(0xf00000f0) {}
495 virtual void g() {printf("F0");}
503 // CHECK-NEXT: 0 | struct F0
504 // CHECK-NEXT: 0 | (F0 vftable pointer)
526 // CHECK-X64-NEXT: 0 | struct F0
527 // CHECK-X64-NEXT: 0 | (F0 vftable pointer)
863 sizeof(F0)+

Completed in 820 milliseconds

1 2 3 4 5