| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 527 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
531 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
532 FMINNUM, FMAXNUM,
533 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that
[all...] |
| BasicTTIImpl.h | 769 ISDs.push_back(ISD::FMINNUM);
[all...] |
| SelectionDAG.h | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 560 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
564 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
565 FMINNUM, FMAXNUM,
566 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that
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| BasicTTIImpl.h | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 308 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break;
372 Opcode = ISD::FMINNUM; break;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 334 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break;
400 Opcode = ISD::FMINNUM; break;
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 205 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
223 setTargetDAGCombine(ISD::FMINNUM);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 378 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
469 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
569 setOperationAction(ISD::FMINNUM, MVT::v2f16, Legal);
590 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
624 setTargetDAGCombine(ISD::FMINNUM);
[all...] |
| AMDGPUISelLowering.cpp | 313 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
446 setOperationAction(ISD::FMINNUM, VT, Expand);
551 case ISD::FMINNUM:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 153 case ISD::FMINNUM: return "fminnum";
|
| LegalizeVectorOps.cpp | 303 case ISD::FMINNUM:
[all...] |
| LegalizeFloatTypes.cpp | 77 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
[all...] |
| LegalizeVectorTypes.cpp | 110 case ISD::FMINNUM:
675 case ISD::FMINNUM:
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| SelectionDAGBuilder.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 176 case ISD::FMINNUM: return "fminnum";
[all...] |
| LegalizeFloatTypes.cpp | 77 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
[all...] |
| LegalizeVectorOps.cpp | 362 case ISD::FMINNUM:
[all...] |
| LegalizeVectorTypes.cpp | 114 case ISD::FMINNUM:
732 case ISD::FMINNUM:
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 115 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
125 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 600 setOperationAction(ISD::FMINNUM, VT, Expand);
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| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 292 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
384 setOperationAction(ISD::FMINNUM, Ty, Legal);
705 ISD::FMINNUM, ISD::FMAXNUM})
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 456 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
461 setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal);
466 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
471 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
476 setOperationAction(ISD::FMINNUM, MVT::f128, Legal);
[all...] |
