| /external/u-boot/board/gdsys/common/ |
| mclink.c | 38 FPGA_SET_REG(k, mc_control, 0x8000);
69 FPGA_SET_REG(0, mc_int, int_status);
72 FPGA_SET_REG(0, mc_tx_address, addr);
73 FPGA_SET_REG(0, mc_tx_data, data);
74 FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14);
75 FPGA_SET_REG(0, mc_control, 0x8001);
103 FPGA_SET_REG(0, mc_tx_address, addr);
104 FPGA_SET_REG(0, mc_tx_cmd,
106 FPGA_SET_REG(0, mc_control, 0x8001);
|
| cmd_ioloop.c | 62 FPGA_SET_REG(fpga, ep.rx_tx_status, status);
67 FPGA_SET_REG(fpga, ep.rx_tx_status, status);
99 FPGA_SET_REG(fpga, ep.transmit_data, *p++);
102 FPGA_SET_REG(fpga, ep.transmit_data, k);
104 FPGA_SET_REG(fpga, ep.rx_tx_control,
153 FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);
155 FPGA_SET_REG(fpga, ep.rx_tx_control,
185 FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
188 FPGA_SET_REG(fpga, ep.device_address, 1);
251 FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE)
[all...] |
| osd.c | 41 FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
43 FPGA_SET_REG(screen, osd0.fld, val); \
47 FPGA_SET_REG(screen, osd0.fld, val)
126 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
248 FPGA_SET_REG(screen - OSD_DH_BASE,
251 FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
253 FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
|
| ihs_mdio.c | 64 FPGA_SET_REG(info->fpga, mdio.control, val);
73 FPGA_SET_REG(info->fpga, mdio.address_data, val);
|
| /external/u-boot/board/gdsys/mpc8308/ |
| hrcon.c | 58 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) function
238 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
243 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
260 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
268 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
389 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
391 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
400 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
410 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
412 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO)
[all...] |
| strider.c | 61 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) function
236 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
291 FPGA_SET_REG(bus, gpio.set, pin);
296 FPGA_SET_REG(bus, gpio.clear, pin);
314 FPGA_SET_REG(bus, control, val | pin);
322 FPGA_SET_REG(bus, control, val & ~pin);
444 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
446 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
455 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
465 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO)
[all...] |
| mpc8308.c | 83 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
|
| /external/u-boot/drivers/i2c/ |
| ihs_i2c.c | 41 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
43 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
47 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
|
| /external/u-boot/include/ |
| gdsys_fpga.h | 20 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
25 #define FPGA_SET_REG(ix, fld, val) \
26 fpga_set_reg((ix), \
|
