/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 154 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 156 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 158 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 172 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, 174 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, 176 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } 189 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 }, 191 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 }, 193 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 }, 195 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 } [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 215 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 217 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 219 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 233 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, 235 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, 237 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } 250 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 }, 252 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 }, 254 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 }, 256 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 } [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64TargetTransformInfo.cpp | 259 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 260 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 261 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 267 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 }, 268 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, 269 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 }, 274 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 275 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 }, 281 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, 282 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 } [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64TargetTransformInfo.cpp | 362 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 363 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 364 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 370 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 }, 371 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, 372 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 }, 377 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 378 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 }, 384 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, 385 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 } [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
ISDOpcodes.h | 385 FP_TO_UINT, [all...] |
/external/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | 542 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 543 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 544 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 545 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 546 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 547 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 610 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 611 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 612 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 613 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 } [all...] |
X86IntrinsicsInfo.h | [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 449 FP_TO_UINT, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 495 FP_TO_UINT, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 300 case ISD::FP_TO_UINT: 391 case ISD::FP_TO_UINT: 482 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) { 483 NewOpc = ISD::FP_TO_UINT; [all...] |
LegalizeVectorTypes.cpp | 90 case ISD::FP_TO_UINT: 441 case ISD::FP_TO_UINT: 649 case ISD::FP_TO_UINT: [all...] |
SelectionDAGDumper.cpp | 257 case ISD::FP_TO_UINT: return "fp_to_uint";
|
LegalizeIntegerTypes.cpp | 115 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 421 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 425 if (N->getOpcode() == ISD::FP_TO_UINT && 426 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 435 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 171 case ISD::FP_TO_UINT:
|
LegalizeVectorTypes.cpp | 84 case ISD::FP_TO_UINT: 461 case ISD::FP_TO_UINT: [all...] |
LegalizeIntegerTypes.cpp | 97 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 354 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 358 if (N->getOpcode() == ISD::FP_TO_UINT && 359 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 368 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 359 case ISD::FP_TO_UINT: 463 case ISD::FP_TO_UINT: 538 // Change FP_TO_UINT to FP_TO_SINT if possible. 539 // TODO: Should we only do this if FP_TO_UINT itself isn't legal? 540 if (NewOpc == ISD::FP_TO_UINT && 550 Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext [all...] |
SelectionDAGDumper.cpp | 300 case ISD::FP_TO_UINT: return "fp_to_uint"; [all...] |
LegalizeVectorTypes.cpp | 93 case ISD::FP_TO_UINT: 467 case ISD::FP_TO_UINT: 705 case ISD::FP_TO_UINT: [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 155 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 156 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 326 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); 328 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); 332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 334 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 336 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand); 386 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 387 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); [all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | 331 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 368 setOperationAction(ISD::FP_TO_UINT, VT, Expand); 722 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | 385 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 407 setOperationAction(ISD::FP_TO_UINT, VT, Expand); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 226 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom); 502 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 507 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 512 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 514 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); 516 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 523 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 529 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 654 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); [all...] |