/external/llvm/lib/Target/Lanai/ |
LanaiInstrInfo.cpp | 509 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); 511 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); 534 // allocator ensure the FalseReg is allocated the same register as operand 0. 535 FalseReg.setImplicit(); 536 NewMI.addOperand(FalseReg);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
LanaiInstrInfo.cpp | 507 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); 509 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); 532 // allocator ensure the FalseReg is allocated the same register as operand 0. 533 FalseReg.setImplicit(); 534 NewMI.add(FalseReg);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86CmovConversion.cpp | 721 unsigned FalseReg = 726 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); 729 FalseReg = FRIt->second; 731 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; [all...] |
X86InstrInfo.h | 347 unsigned FalseReg) const override;
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/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.h | 159 unsigned FalseReg) const override;
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AArch64InstrInfo.cpp | 368 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, 373 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 389 else if (canFoldIntoCSel(MRI, FalseReg)) 411 unsigned TrueReg, unsigned FalseReg) const { 517 // FalseReg, so we need to invert the condition. 519 TrueReg = FalseReg; 521 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); 525 FalseReg = NewVReg; 534 MRI.constrainRegClass(FalseReg, RC); 537 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.h | 182 unsigned FalseReg) const override;
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PPCInstrInfo.cpp | 687 unsigned TrueReg, unsigned FalseReg, 703 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 729 unsigned FalseReg) const { 739 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 740 assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, 792 SecondReg = SwapOps ? TrueReg : FalseReg; [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
SystemZInstrInfo.h | 219 unsigned FalseReg) const override;
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SystemZInstrInfo.cpp | 636 unsigned TrueReg, unsigned FalseReg, 648 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 672 unsigned FalseReg) const { 690 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); 692 FalseReg = FReg; 700 .addReg(FalseReg).addReg(TrueReg) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.cpp | 745 unsigned TrueReg, unsigned FalseReg, 758 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 784 unsigned FalseReg) const { 791 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 792 assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, 844 SecondReg = SwapOps ? TrueReg : FalseReg; [all...] |
PPCInstrInfo.h | 241 unsigned FalseReg) const override;
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/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | 672 /// instruction that chooses between TrueReg and FalseReg based on the 676 /// FalseReg, and Cond to the destination register. In most cases, a select 684 /// @param FalseReg Virtual register to select when Cond is false. 687 /// @param FalseCycles Latency from FalseReg to select output. 690 unsigned TrueReg, unsigned FalseReg, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
TargetInstrInfo.h | [all...] |
/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyFastISel.cpp | 728 unsigned FalseReg = getRegForValue(Select->getFalseValue()); 729 if (FalseReg == 0) 733 std::swap(TrueReg, FalseReg); 764 .addReg(FalseReg) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.h | 189 unsigned FalseReg) const override;
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AArch64InstrInfo.cpp | 488 unsigned TrueReg, unsigned FalseReg, 494 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 510 else if (canFoldIntoCSel(MRI, FalseReg)) 532 unsigned TrueReg, unsigned FalseReg) const { 638 // FalseReg, so we need to invert the condition. 640 TrueReg = FalseReg; 642 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); 646 FalseReg = NewVReg; 655 MRI.constrainRegClass(FalseReg, RC); 660 .addReg(FalseReg) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIInstrInfo.cpp | 684 unsigned FalseReg) const { 694 .addReg(FalseReg) 706 .addReg(FalseReg) 717 .addReg(FalseReg) 729 .addReg(FalseReg) 742 .addReg(FalseReg) 755 .addReg(FalseReg) 769 .addReg(FalseReg) [all...] |
SIInstrInfo.h | 264 unsigned TrueReg, unsigned FalseReg, 271 unsigned TrueReg, unsigned FalseReg) const override; 276 unsigned TrueReg, unsigned FalseReg) const; [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
WebAssemblyISelLowering.cpp | 244 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; 249 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); 291 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg) 298 .addReg(FalseReg) [all...] |
WebAssemblyFastISel.cpp | 865 unsigned FalseReg = getRegForValue(Select->getFalseValue()); 866 if (FalseReg == 0) 870 std::swap(TrueReg, FalseReg); 905 .addReg(FalseReg) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
ARMInstructionSelector.cpp | 640 auto FalseReg = MIB->getOperand(3).getReg(); 642 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && 647 .addUse(FalseReg) [all...] |
ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 328 unsigned FalseReg) const override;
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/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.cpp | [all...] |