| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/ |
| BoardGpios.c | 420 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL, PlatformCfioDataPtr->Use_Sel_SC0);
425 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL , PlatformCfioDataPtr->GP_Lvl_SC0);
430 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL, PlatformCfioDataPtr->Io_Sel_SC0);
435 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TPE, PlatformCfioDataPtr->TPE_SC0);
440 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TNE, PlatformCfioDataPtr->TNE_SC0);
445 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TS, PlatformCfioDataPtr->TS_SC0);
450 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL2, PlatformCfioDataPtr->Use_Sel_SC1);
455 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2, PlatformCfioDataPtr->GP_Lvl_SC1);
460 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL2, PlatformCfioDataPtr->Io_Sel_SC1);
465 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL3, PlatformCfioDataPtr->Use_Sel_SC2);
[all...] |
| /external/u-boot/arch/x86/include/asm/arch-braswell/ |
| iomap.h | 44 #define GPIO_BASE_ADDRESS 0x500
|
| /external/u-boot/arch/x86/include/asm/arch-broadwell/ |
| iomap.h | 39 #define GPIO_BASE_ADDRESS 0x1400
|
| /external/u-boot/arch/x86/include/asm/arch-quark/ |
| iomap.h | 37 #define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/ |
| PlatformBaseAddresses.h | 56 #define GPIO_BASE_ADDRESS 0x0500
|
| /external/u-boot/arch/x86/include/asm/arch-baytrail/ |
| iomap.h | 88 #define GPIO_BASE_ADDRESS 0x0500
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| BoardId.c | 162 Data8 = IoRead8(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2);
|
| /external/u-boot/arch/x86/include/asm/arch-quark/acpi/ |
| southcluster.asl | 153 IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformSmm/ |
| Platform.c | 628 Data32 = IoRead32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL);
630 IoWrite32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL, Data32);
|
| /external/u-boot/arch/x86/cpu/broadwell/ |
| sdram.c | 47 pei_data->gpiobase = GPIO_BASE_ADDRESS;
|
| pch.c | 45 dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| PlatformEarlyInit.c | 392 IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,
393 (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));
[all...] |
| PchInitPeim.c | 661 PchPlatformPolicyPpi->GpioBase = GPIO_BASE_ADDRESS;
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformPei/ |
| Platform.c | 571 (UINT16)((GPIO_BASE_ADDRESS & B_PCH_LPC_GPIO_BASE_BAR) | B_PCH_LPC_GPIO_BASE_EN)
[all...] |
