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Searched
refs:GetLane
(Results
1 - 11
of
11
) sorted by null
/external/gemmlowp/internal/
output_msa.h
251
*dst->data(row + 0, col) =
GetLane
<0>(src.buf.reg[0]);
252
*dst->data(row + 1, col) =
GetLane
<1>(src.buf.reg[0]);
253
*dst->data(row + 2, col) =
GetLane
<2>(src.buf.reg[0]);
254
*dst->data(row + 3, col) =
GetLane
<3>(src.buf.reg[0]);
267
*dst->data(row + 0, col) =
GetLane
<0>(src.buf.reg[0]);
268
*dst->data(row + 1, col) =
GetLane
<1>(src.buf.reg[0]);
269
*dst->data(row + 2, col) =
GetLane
<2>(src.buf.reg[0]);
270
*dst->data(row + 3, col) =
GetLane
<3>(src.buf.reg[0]);
271
*dst->data(row + 4, col) =
GetLane
<0>(src.buf.reg[1]);
272
*dst->data(row + 5, col) =
GetLane
<1>(src.buf.reg[1])
[
all
...]
output_sse.h
189
*dst->data(row + 0, col) =
GetLane
<0>(src.buf.reg[0]);
190
*dst->data(row + 1, col) =
GetLane
<1>(src.buf.reg[0]);
191
*dst->data(row + 2, col) =
GetLane
<2>(src.buf.reg[0]);
192
*dst->data(row + 3, col) =
GetLane
<3>(src.buf.reg[0]);
205
*dst->data(row + 0, col) =
GetLane
<0>(src.buf.reg[0]);
206
*dst->data(row + 1, col) =
GetLane
<1>(src.buf.reg[0]);
207
*dst->data(row + 2, col) =
GetLane
<2>(src.buf.reg[0]);
208
*dst->data(row + 3, col) =
GetLane
<3>(src.buf.reg[0]);
209
*dst->data(row + 4, col) =
GetLane
<0>(src.buf.reg[1]);
210
*dst->data(row + 5, col) =
GetLane
<1>(src.buf.reg[1])
[
all
...]
simd_wrappers_sse.h
73
std::int32_t
GetLane
(Int32x4 value) {
simd_wrappers_msa.h
97
std::int32_t
GetLane
(Int32x4 value) {
simd_wrappers_neon.h
68
std::int32_t
GetLane
(Int32x4 value) {
/art/compiler/optimizing/
common_arm.h
160
DCHECK(s.Is(d.
GetLane
(0)) || s.Is(d.
GetLane
(1)));
/external/vixl/src/aarch64/
simulator-aarch64.h
124
return
GetLane
<T>(0);
130
T
GetLane
(int lane) const {
136
VIXL_DEPRECATED("
GetLane
", T Get(int lane) const) {
137
return
GetLane
(lane);
211
element = register_.
GetLane
<int8_t>(index);
214
element = register_.
GetLane
<int16_t>(index);
217
element = register_.
GetLane
<int32_t>(index);
220
element = register_.
GetLane
<int64_t>(index);
233
element = register_.
GetLane
<uint8_t>(index);
236
element = register_.
GetLane
<uint16_t>(index)
[
all
...]
simulator-aarch64.cc
844
value = ReadVRegister(code).
GetLane
<uint16_t>(lane);
847
value = ReadVRegister(code).
GetLane
<float>(lane);
850
value = ReadVRegister(code).
GetLane
<double>(lane);
[
all
...]
/external/vixl/src/aarch32/
assembler-aarch32.cc
520
if ((lane.
GetLane
() & 7) != lane.
GetLane
()) {
523
SetEncodingValue(0x8 | lane.
GetLane
());
526
if ((lane.
GetLane
() & 3) != lane.
GetLane
()) {
529
SetEncodingValue(0x1 | (lane.
GetLane
() << 1));
532
if ((lane.
GetLane
() & 7) != lane.
GetLane
()) {
535
SetEncodingValue(0x18 | lane.
GetLane
());
538
if ((lane.
GetLane
() & 3) != lane.GetLane())
[
all
...]
instructions-aarch32.h
224
SRegister
GetLane
(uint32_t lane) const {
330
uint32_t
GetLane
() const { return lane_; }
359
if (lane.
GetLane
() == static_cast<uint32_t>(-1)) return os << "??]";
360
return os << lane.
GetLane
() << "]";
[
all
...]
disasm-aarch32.cc
79
int
GetLane
() const { return lane_; }
[
all
...]
Completed in 163 milliseconds