| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 240 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
517 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
525 unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
628 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
640 return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
652 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
682 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
[all...] |
| HexagonISelLoweringHVX.cpp | 261 if (Vec.getOpcode() == HexagonISD::QCAT)
386 return DAG.getNode(HexagonISD::VSPLATW, dl, VecTy, SplatV);
409 SDValue N = DAG.getNode(HexagonISD::VINSERTW0, dl, VecTy,
411 SDValue M = DAG.getNode(HexagonISD::VINSERTW0, dl, VecTy,
413 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, S});
414 HalfV1 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {M, S});
417 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy,
439 SDValue T = DAG.getNode(HexagonISD::Q2V, dl, ByteTy, PredV);
457 SDValue M = DAG.getNode(HexagonISD::Q2V, dl, ByteTy, Q);
477 : DAG.getNode(HexagonISD::P2D, dl, MVT::i64, PredV)
[all...] |
| HexagonISelDAGToDAG.cpp | 766 unsigned OpcCarry = N->getOpcode() == HexagonISD::ADDC ? Hexagon::A4_addp_c
[all...] |
| HexagonISelDAGToDAGHVX.cpp | 940 case HexagonISD::VZERO:
941 case HexagonISD::VSPLATW:
946 if (AddrOpc == HexagonISD::AT_PCREL || AddrOpc == HexagonISD::CP)
954 N->use_begin()->getOpcode() == HexagonISD::VSPLATW;
[all...] |
| HexagonISelLowering.h | 32 namespace HexagonISD {
93 } // end namespace HexagonISD
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 592 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
[all...] |
| HexagonISelLowering.h | 28 namespace HexagonISD {
|
| HexagonISelDAGToDAG.cpp | [all...] |
