| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| PlatformEarlyInit.c | 347 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
348 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
349 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
350 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
351 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
352 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
353 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
354 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
355 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
356 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
[all...] |
| PchInitPeim.c | 468 MmioOr32 (IO_BASE_ADDRESS + 0x0520, 0x01); // UART3_RXD-L
469 MmioOr32 (IO_BASE_ADDRESS + 0x0530, 0x01); // UART3_TXD-0
476 MmioAnd32 (IO_BASE_ADDRESS + 0x0520, ~(UINT32)0x07);
477 MmioAnd32 (IO_BASE_ADDRESS + 0x0530, ~(UINT32)0x07);
486 MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);
487 MmioOr8 (IO_BASE_ADDRESS + 0x0090, 0x01);
488 MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);
489 MmioOr8 (IO_BASE_ADDRESS + 0x00D0, 0x01);
503 MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);
504 MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);
[all...] |
| BootMode.c | 185 GpioValue = MmioRead32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + PMU_PWRBTN_B_OFFSET); // The value of GPIOS_16 (PMU_PWRBTN_B)
|
| /external/u-boot/arch/x86/cpu/baytrail/ |
| valleyview.c | 15 #define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
|
| early_uart.c | 27 #define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
30 #define IO_BASE_ADDRESS 0xfed0c000
|
| /external/u-boot/arch/x86/include/asm/arch-braswell/ |
| iomap.h | 32 #define IO_BASE_ADDRESS 0xfed80000
|
| gpio.h | 173 ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
207 ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/ |
| UartInit.c | 40 #define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address
188 MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));
189 MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L
190 MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));
191 MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L
|
| /external/u-boot/arch/x86/include/asm/arch-baytrail/acpi/ |
| gpio.asl | 28 Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
57 Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
86 Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
|
| /external/u-boot/arch/x86/cpu/braswell/ |
| early_uart.c | 32 #define IO_BASE_ADDRESS 0xfed80000
36 return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/ |
| PlatformBaseAddresses.h | 62 #define IO_BASE_ADDRESS 0xFED0C000 // IO Memory Base Address
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/MonoStatusCode/ |
| PlatformStatusCode.c | 356 MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));
357 MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L
358 MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));
359 MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L
|
| /external/u-boot/arch/x86/include/asm/arch-baytrail/ |
| iomap.h | 67 #define IO_BASE_ADDRESS 0xfed0c000
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/ |
| BoardGpios.c | 251 mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
252 mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| Platform.c | 309 mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
310 mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
613 mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/ |
| I2CLibPei.c | 118 I2CLibPeiMmioWrite32(IO_BASE_ADDRESS+I2CGPIO[Index], 0x2003CC81);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformPei/ |
| Platform.c | 597 (UINT32)((IO_BASE_ADDRESS & B_PCH_LPC_IO_BASE_BAR) | B_PCH_LPC_IO_BASE_EN)
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/PlatformBdsLib/ |
| BdsPlatform.c | [all...] |
