| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 114 int64_t imms = Op3.getImm(); local
115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
117 shift = 31 - imms;
118 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
119 ((imms + 1 == immr))) {
121 shift = 63 - imms;
122 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
125 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
128 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 123 int64_t imms = Op3.getImm(); local
124 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
126 shift = 31 - imms;
127 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
128 ((imms + 1 == immr))) {
130 shift = 63 - imms;
131 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
134 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
137 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64FastISel.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64FastISel.cpp | [all...] |
| /external/capstone/arch/AArch64/ |
| AArch64InstPrinter.c | 140 int64_t imms = MCOperand_getImm(Op3); local
142 if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
144 shift = 31 - imms;
145 } else if (Opcode == AArch64_UBFMXri && imms != 0x3f &&
146 ((imms + 1 == immr))) {
148 shift = 63 - imms;
149 } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) {
152 } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) {
155 } else if (Opcode == AArch64_SBFMWri && imms == 0x1f)
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 956 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
957 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
958 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
960 return imms << ImmS_offset;
973 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
975 DCHECK(is_uint6(imms));
976 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
978 return imms << ImmSetBits_offset;
[all...] |
| assembler-arm64.cc | [all...] |
| constants-arm64.h | 192 V_(ImmS, 15, 10, Bits) \
[all...] |
| disasm-arm64.cc | 421 unsigned s = instr->ImmS();
[all...] |
| simulator-arm64.cc | 894 unsigned lsb = instr->ImmS();
[all...] |
| assembler-arm64.h | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.cc | 663 unsigned imms) {
667 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd));
674 unsigned imms) {
678 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd));
685 unsigned imms) {
689 ImmS(imms, rn.GetSizeInBits()) | Rn(rn) | Rd(rd));
700 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.GetSizeInBits()) | Rn(rn)
[all...] |
| assembler-aarch64.h | 728 unsigned imms);
734 unsigned imms);
740 unsigned imms);
[all...] |
| constants-aarch64.h | 91 V_(ImmS, 15, 10, ExtractBits) \
[all...] |
