OpenGrok
Home
Sort by relevance
Sort by last modified time
Full Search
Definition
Symbol
File Path
History
|
|
Help
Searched
refs:InstrDesc
(Results
1 - 19
of
19
) sorted by null
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
InstrBuilder.h
32
/// Every llvm-mca Instruction is described by an object of class
InstrDesc
.
33
/// An
InstrDesc
describes which registers are read/written by the instruction,
37
/// descriptors (i.e.
InstrDesc
objects).
48
llvm::DenseMap<unsigned short, std::unique_ptr<const
InstrDesc
>> Descriptors;
49
llvm::DenseMap<const llvm::MCInst *, std::unique_ptr<const
InstrDesc
>>
52
const
InstrDesc
&createInstrDescImpl(const llvm::MCInst &MCI);
56
void populateWrites(
InstrDesc
&ID, const llvm::MCInst &MCI,
58
void populateReads(
InstrDesc
&ID, const llvm::MCInst &MCI,
70
const
InstrDesc
&getOrCreateInstrDesc(const llvm::MCInst &MCI);
LSUnit.h
24
struct
InstrDesc
;
RetireStage.cpp
49
const
InstrDesc
&Desc = Inst.getDesc();
Scheduler.cpp
151
bool ResourceManager::canBeIssued(const
InstrDesc
&Desc) const {
162
bool ResourceManager::mustIssueImmediately(const
InstrDesc
&Desc) {
178
const
InstrDesc
&Desc,
239
const
InstrDesc
&Desc = IR.getInstruction()->getDesc();
264
const
InstrDesc
&D = IS->getDesc();
282
const
InstrDesc
&Desc = IR.getInstruction()->getDesc();
299
const
InstrDesc
&Desc = IS->getDesc();
318
const
InstrDesc
&D = Entry.second->getDesc();
335
const
InstrDesc
&D = I->second->getDesc();
393
const
InstrDesc
&Desc = IR.getInstruction()->getDesc()
[
all
...]
InstrBuilder.cpp
29
static void initializeUsedResources(
InstrDesc
&ID,
143
static void computeMaxLatency(
InstrDesc
&ID, const MCInstrDesc &MCDesc,
158
void InstrBuilder::populateWrites(
InstrDesc
&ID, const MCInst &MCI,
270
void InstrBuilder::populateReads(
InstrDesc
&ID, const MCInst &MCI,
318
const
InstrDesc
&InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
356
std::unique_ptr<
InstrDesc
> ID = llvm::make_unique<
InstrDesc
>();
395
const
InstrDesc
&InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
407
const
InstrDesc
&D = getOrCreateInstrDesc(MCI);
Instruction.h
239
/// Helper used by class
InstrDesc
to describe how hardware resources
255
struct
InstrDesc
{
282
const
InstrDesc
&Desc;
319
Instruction(const
InstrDesc
&D)
329
const
InstrDesc
&getDesc() const { return Desc; }
InstructionTables.cpp
26
const
InstrDesc
&Desc = IR.getInstruction()->getDesc();
SummaryView.cpp
49
const
InstrDesc
&Desc = Inst.getDesc();
DispatchStage.cpp
93
const
InstrDesc
&Desc = IS.getDesc();
140
const
InstrDesc
&Desc = IR.getInstruction()->getDesc();
ExecuteStage.cpp
59
const
InstrDesc
&Desc = IR.getInstruction()->getDesc();
108
const
InstrDesc
&Desc = IR.getInstruction()->getDesc();
Scheduler.h
362
bool mustIssueImmediately(const
InstrDesc
&Desc);
364
bool canBeIssued(const
InstrDesc
&Desc) const;
367
const
InstrDesc
&Desc,
LSUnit.cpp
55
const
InstrDesc
&Desc = IR.getInstruction()->getDesc();
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-cfi-verify/lib/
FileAnalysis.cpp
167
const auto &
InstrDesc
= MII->get(InstrMeta.Instruction.getOpcode());
168
return
InstrDesc
.isTrap();
178
const auto &
InstrDesc
= MII->get(InstrMeta.Instruction.getOpcode());
179
if (
InstrDesc
.mayAffectControlFlow(InstrMeta.Instruction, *RegisterInfo))
180
return
InstrDesc
.isConditionalBranch();
193
const auto &
InstrDesc
= MII->get(InstrMeta.Instruction.getOpcode());
195
if (
InstrDesc
.mayAffectControlFlow(InstrMeta.Instruction, *RegisterInfo)) {
196
if (
InstrDesc
.isConditionalBranch())
269
const auto &
InstrDesc
= MII->get(InstrMetaPtr->Instruction.getOpcode());
270
if (!
InstrDesc
.mayAffectControlFlow(InstrMetaPtr->Instruction, *RegisterInfo)
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
BenchmarkRunner.cpp
39
const llvm::MCInstrDesc &
InstrDesc
= State.getInstrInfo().get(Opcode);
41
if (
InstrDesc
.isPseudo())
43
if (
InstrDesc
.isBranch() ||
InstrDesc
.isIndirectBranch())
46
if (
InstrDesc
.isCall() ||
InstrDesc
.isReturn())
Latency.cpp
85
const auto &
InstrDesc
= State.getInstrInfo().get(Opcode);
86
if (auto E = isInfeasible(
InstrDesc
))
88
const Instruction Instr(
InstrDesc
, RATC);
Uops.cpp
136
const auto &
InstrDesc
= State.getInstrInfo().get(Opcode);
137
if (auto E = isInfeasible(
InstrDesc
))
139
const Instruction Instr(
InstrDesc
, RATC);
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/X86/
Target.cpp
40
const auto &
InstrDesc
= InstrInfo.get(Opcode);
41
const unsigned FPInstClass =
InstrDesc
.TSFlags & llvm::X86II::FPTypeMask;
42
const Instruction Instr(
InstrDesc
, this->RATC);
/external/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp
[
all
...]
Completed in 258 milliseconds