| /external/swiftshader/third_party/subzero/pydir/ |
| gen_arm32_reg_tables.py | 20 IsFP32=0, IsFP64=0, IsVec128=0, Aliases=None):
24 assert not (IsFP32 and IsFP64)
25 assert not (IsFP32 and IsVec128)
27 assert not ((IsGPR) and (IsFP32 or IsFP64 or IsVec128))
54 'IsFP32', 'IsFP64', 'IsVec128'))
110 Reg( 's0', 0, IsScratch=1, CCArg=1, IsFP32=1, Aliases= 's0, d0 , q0'),
111 Reg( 's1', 1, IsScratch=1, CCArg=2, IsFP32=1, Aliases= 's1, d0 , q0'),
112 Reg( 's2', 2, IsScratch=1, CCArg=3, IsFP32=1, Aliases= 's2, d1 , q0'),
113 Reg( 's3', 3, IsScratch=1, CCArg=4, IsFP32=1, Aliases= 's3, d1 , q0'),
114 Reg( 's4', 4, IsScratch=1, CCArg=5, IsFP32=1, Aliases= 's4, d2 , q1')
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceRegistersARM32.h | 31 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
45 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
56 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
67 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
78 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
96 unsigned IsFP32 : 1;
118 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
133 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
162 return RegTable[RegNum].IsFP32;
168 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
[all...] |
| IceTargetLoweringARM32.cpp | 111 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
114 isInt, isI64Pair, isFP32, isFP64, isVec128, \
249 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
258 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
267 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
276 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
285 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
326 Float32Registers[i] = Entry.IsFP32;
346 } else if (Entry.IsFP32) {
[all...] |
