| /external/swiftshader/third_party/subzero/pydir/ |
| gen_arm32_reg_tables.py | 19 IsStackPtr=0, IsFramePtr=0, IsGPR=0, IsInt=0, IsI64Pair=0,
21 assert (not IsInt) or IsGPR
22 assert (not IsI64Pair) or (not IsGPR)
27 assert not ((IsGPR) and (IsFP32 or IsFP64 or IsVec128))
28 assert (not IsFramePtr) or IsGPR
29 assert (not IsStackPtr) or IsGPR
82 Reg( 'r0', 0, IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1, Aliases= 'r0, r0r1'),
83 Reg( 'r1', 1, IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1, Aliases= 'r1, r0r1'),
84 Reg( 'r2', 2, IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1, Aliases= 'r2, r2r3'),
85 Reg( 'r3', 3, IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1, Aliases= 'r3, r2r3')
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceRegistersMIPS32.h | 75 bool IsGPR = ((int(Reg_GPR_First) <= int(RegNum)) &&
79 return IsGPR;
|
| IceRegistersARM32.h | 31 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
45 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
56 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
67 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
78 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
93 unsigned IsGPR : 1;
112 return RegTable[RegNum].IsGPR;
118 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
119 +(isGPR)
133 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
[all...] |
| IceAssemblerX86Base.h | 826 static constexpr bool IsGPR
[all...] |
| IceTargetLoweringARM32.cpp | 111 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
113 name, encode, cc_arg, scratch, preserved, stackptr, frameptr, isGPR, \
249 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
258 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
267 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
276 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
285 isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
342 if (Entry.IsGPR) {
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 232 bool expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR, bool Is64FPU,
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
