| /external/u-boot/drivers/ddr/marvell/a38x/ |
| ddr3_training.c | 146 {0x1034, 0x38000, MASK_ALL_BITS},
147 {0x1038, 0x0, MASK_ALL_BITS},
148 {0x10b0, 0x0, MASK_ALL_BITS},
149 {0x10b8, 0x0, MASK_ALL_BITS},
150 {0x10c0, 0x0, MASK_ALL_BITS},
151 {0x10f0, 0x0, MASK_ALL_BITS},
152 {0x10f4, 0x0, MASK_ALL_BITS},
153 {0x10f8, 0xff, MASK_ALL_BITS},
154 {0x10fc, 0xffff, MASK_ALL_BITS},
155 {0x1130, 0x0, MASK_ALL_BITS},
[all...] |
| ddr3_training_bist.c | 45 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_length, MASK_ALL_BITS);
55 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_OFFS_REG, offset, MASK_ALL_BITS);
65 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS);
87 MASK_ALL_BITS);
93 MASK_ALL_BITS);
100 MASK_ALL_BITS);
106 MASK_ALL_BITS);
236 ddr3_tip_if_read(0, ACCESS_TYPE_UNICAST, 0, reg_map[subphy], &read_data, MASK_ALL_BITS);
433 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS);
466 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_len, MASK_ALL_BITS);
[all...] |
| ddr3_training_leveling.c | 91 MASK_ALL_BITS));
134 MASK_ALL_BITS));
221 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS);
278 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS));
287 ODPG_DATA_CTRL_REG, 0x0, MASK_ALL_BITS));
321 MASK_ALL_BITS));
466 MASK_ALL_BITS));
509 MASK_ALL_BITS));
594 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS);
635 MASK_ALL_BITS));
[all...] |
| ddr3_training_ip_def.h | 41 #define MASK_ALL_BITS 0xffffffff
|
| ddr3_training_pbs.c | 61 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS));
72 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS);
104 res0, MASK_ALL_BITS));
223 res0, MASK_ALL_BITS));
412 res0, MASK_ALL_BITS));
534 res0, MASK_ALL_BITS));
637 res0, MASK_ALL_BITS));
869 MASK_ALL_BITS));
875 ODPG_WR_RD_MODE_ENA_REG, 0xffff, MASK_ALL_BITS));
|
| mv_ddr_plat.c | 248 if (mask != MASK_ALL_BITS) {
249 dunit_read(addr, MASK_ALL_BITS, ®_val);
289 dunit_read(ODPG_ENABLE_REG, MASK_ALL_BITS, &data);
332 dunit_read(DRAM_INIT_CTRL_STATUS_REG, MASK_ALL_BITS, &data);
580 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, ®_val);
600 dunit_write(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, reg_val);
602 dunit_write(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, reg_val);
624 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, ®_val);
630 dunit_read(PHY_REG_FILE_ACCESS_REG, MASK_ALL_BITS, ®_val);
[all...] |
| ddr3_training_ip_engine.c | 414 MASK_ALL_BITS));
561 ODPG_DATA_CTRL_REG, 0, MASK_ALL_BITS);
586 MASK_ALL_BITS));
592 MASK_ALL_BITS));
599 MASK_ALL_BITS));
605 MASK_ALL_BITS));
610 MASK_ALL_BITS));
615 ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS));
797 MASK_ALL_BITS));
[all...] |
| ddr3_debug.c | 124 MASK_ALL_BITS));
564 read_data, MASK_ALL_BITS));
569 read_data, MASK_ALL_BITS));
574 read_data, MASK_ALL_BITS));
606 read_data, MASK_ALL_BITS));
[all...] |
| ddr3_training_centralization.c | 84 DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS));
484 MASK_ALL_BITS));
522 MASK_ALL_BITS));
|
| ddr3_training_hw_algo.c | 58 data_read, MASK_ALL_BITS));
|
