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    Searched refs:MAX_CS_NUM (Results 1 - 7 of 7) sorted by null

  /external/u-boot/drivers/ddr/marvell/a38x/
xor.c 17 static u32 ui_xor_regs_base_backup[MAX_CS_NUM + 1];
18 static u32 ui_xor_regs_mask_backup[MAX_CS_NUM + 1];
26 for (ui = 0; ui < MAX_CS_NUM + 1; ui++)
29 for (ui = 0; ui < MAX_CS_NUM + 1; ui++)
98 for (ui = 0; ui < MAX_CS_NUM + 1; ui++)
101 for (ui = 0; ui < MAX_CS_NUM + 1; ui++)
ddr3_training_ip.h 13 #define MAX_CS_NUM 4
ddr3_training_hw_algo.c 46 u32 read_sample[MAX_CS_NUM];
61 for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) {
ddr3_debug.c 89 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
90 u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
91 u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
824 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
    [all...]
mv_ddr_plat.c 1038 for (cs = 0; cs < MAX_CS_NUM; cs++) {
1127 for (cs = 0; cs < MAX_CS_NUM; cs++) {
1174 for (cs = 0; cs < MAX_CS_NUM; cs++) {
    [all...]
ddr3_training_pbs.c 13 u8 result_mat_rx_dqs[MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
20 u32 pbsdelay_per_pup[NUM_OF_PBS_MODES][MAX_INTERFACE_NUM][MAX_BUS_NUM][MAX_CS_NUM];
ddr3_training.c 329 for (cs = 0; cs < MAX_CS_NUM; cs++) {
    [all...]

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