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    Searched refs:MCFSIM_DACR0 (Results 1 - 4 of 4) sorted by null

  /external/u-boot/board/freescale/m5249evb/
m5249evb.c 68 mbar_writeLong(MCFSIM_DACR0, 0x00003324);
74 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
79 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
83 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
  /external/u-boot/board/freescale/m5253demo/
m5253demo.c 42 mbar_writeLong(MCFSIM_DACR0, 0x00003224);
51 mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
61 mbar_writeLong(MCFSIM_DACR0,
62 mbar_readLong(MCFSIM_DACR0) | 0x8000);
69 mbar_writeLong(MCFSIM_DACR0,
70 mbar_readLong(MCFSIM_DACR0) | 0x0040);
  /external/u-boot/board/freescale/m5253evbe/
m5253evbe.c 39 mbar_writeLong(MCFSIM_DACR0, 0x00002320);
47 mbar_writeLong(MCFSIM_DACR0, 0x00002328);
55 mbar_writeLong(MCFSIM_DACR0,
56 mbar_readLong(MCFSIM_DACR0) | 0x8000);
63 mbar_writeLong(MCFSIM_DACR0,
64 mbar_readLong(MCFSIM_DACR0) | 0x0040);
  /external/u-boot/arch/m68k/include/asm/
m5249.h 64 #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */

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