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    Searched refs:MCFSIM_PLLCR (Results 1 - 2 of 2) sorted by null

  /external/u-boot/arch/m68k/cpu/mcf52x2/
speed.c 28 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
47 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
48 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
50 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
  /external/u-boot/arch/m68k/include/asm/
m5249.h 108 #define MCFSIM_PLLCR 0x180 /* PLL Control register */

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