| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 254 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
290 unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
|
| MipsInstrInfo.cpp | 118 Opc = Mips::MFLO, SrcReg = 0;
|
| /external/v8/src/compiler/mips/ |
| instruction-scheduler-mips.cc | 420 MFLO = 1,
1024 return Latency::DIV + Latency::MFLO;
1030 return 1 + Latency::DIV + Latency::MFLO;
1040 return Latency::DIVU + Latency::MFLO;
1046 return 1 + Latency::DIVU + Latency::MFLO;
[all...] |
| /external/v8/src/compiler/mips64/ |
| instruction-scheduler-mips64.cc | 451 MFLO = 1,
501 latency = Latency::DMULT + Latency::MFLO;
569 latency = Latency::DDIV + Latency::MFLO;
582 latency = Latency::DDIVU + Latency::MFLO;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
238 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
350 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
|
| MipsISelLowering.h | 78 MFLO,
|
| MipsSEFrameLowering.cpp | 205 // mflo $vr0, src
237 // mflo $vr0, src
800 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;
[all...] |
| MipsSEISelLowering.cpp | 445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
[all...] |
| MipsFastISel.cpp | [all...] |
| MipsISelLowering.cpp | 128 case MipsISD::MFLO: return "MipsISD::MFLO";
484 // insert MFLO
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeMIPS_64.c | 466 return push_inst(compiler, MFLO | D(dst), DR(dst));
469 return push_inst(compiler, MFLO | D(dst), DR(dst));
474 FAIL_IF(push_inst(compiler, MFLO | D(dst), DR(dst)));
|
| sljitNativeMIPS_32.c | 375 return push_inst(compiler, MFLO | D(dst), DR(dst));
380 FAIL_IF(push_inst(compiler, MFLO | D(dst), DR(dst)));
|
| sljitNativeMIPS_common.c | 160 #define MFLO (HI(0) | LO(18))
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 105 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
311 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
428 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
[all...] |
| MipsISelLowering.h | 129 MFLO,
|
| MipsSEFrameLowering.cpp | 225 // mflo $vr0, src
257 // mflo $vr0, src
823 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;
[all...] |
| MipsFastISel.cpp | [all...] |
| MipsISelLowering.cpp | 209 case MipsISD::MFLO: return "MipsISD::MFLO";
580 // insert MFLO
[all...] |
| MipsSEISelLowering.cpp | [all...] |
| /external/v8/src/mips/ |
| constants-mips.h | 518 MFLO = ((2U << 3) + 2),
[all...] |
| assembler-mips.cc | 2463 void Assembler::mflo(Register rd) { function in class:v8::internal::Assembler
[all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 500 MFLO = ((2U << 3) + 2),
[all...] |
| assembler-mips64.cc | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
