/external/u-boot/arch/arm/mach-davinci/ |
lxt972.c | 92 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 97 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
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/external/u-boot/drivers/net/phy/ |
xilinx_phy.c | 71 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 120 temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 122 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp);
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et1011c.c | 30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET);
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aquantia.c | 24 u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); 32 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); 40 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, 56 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); 95 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
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natsemi.c | 21 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 57 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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davicom.c | 28 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE);
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phy.c | 123 * Description: Configures MII_BMCR to force speed/duplex 142 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); 155 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 165 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); 195 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 367 u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 798 if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) { 811 reg = phy_read(phydev, devad, MII_BMCR); 813 reg = phy_read(phydev, devad, MII_BMCR);
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marvell.c | 135 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 143 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 511 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 513 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); 612 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 614 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
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mscc.c | 253 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 254 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (reg_val | BMCR_RESET)); 256 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 259 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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broadcom.c | 137 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 139 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
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realtek.c | 82 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 128 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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micrel_ksz90x1.c | 354 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 356 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
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/external/u-boot/drivers/qe/ |
uec_phy.c | 259 ctrl = uec_phy_read(mii_info, MII_BMCR); 289 uec_phy_write(mii_info, MII_BMCR, ctrl); 297 ctl = uec_phy_read(mii_info, MII_BMCR); 299 uec_phy_write(mii_info, MII_BMCR, ctl); 334 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); 511 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); 583 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) | 586 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) [all...] |
/external/u-boot/common/ |
miiphyutil.c | 354 if (miiphy_read(devname, addr, MII_BMCR, ®) != 0) { 358 if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { 372 if (miiphy_read(devname, addr, MII_BMCR, ®) != 0) { 420 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { 483 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
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/external/u-boot/board/egnite/ethernut5/ |
ethernut5.c | 174 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
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/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Phy/MvPhyDxe/ |
MvPhyDxe.c | 73 Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg);
75 Mdio->Write(Mdio, PhyAddr, MII_BMCR, Reg);
78 Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg);
161 Mdio->Read(Mdio, PhyDev->Addr, MII_BMCR, &Reg);
164 Mdio->Write(Mdio, PhyDev->Addr, MII_BMCR, Reg);
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MvPhyDxe.h | 37 #define MII_BMCR 0x00 /* Basic mode control Register */
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/external/u-boot/cmd/ |
mii.c | 21 { MII_BMCR, "PHY control register" }, 198 if ((regno == MII_BMCR) && (pdesc->lo == 6)) { 210 else if ((regno == MII_BMCR) && (pdesc->lo == 8)) {
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/external/u-boot/drivers/net/ |
smc911x.c | 87 smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET); 90 smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE |
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davinci_emac.c | 326 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 331 davinci_eth_phy_write(phy_addr, MII_BMCR, val); 340 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) 353 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
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ax88180.c | 116 ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE)); 119 while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) { 351 bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
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/bionic/libc/kernel/uapi/linux/ |
mii.h | 23 #define MII_BMCR 0x00
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/external/kernel-headers/original/uapi/linux/ |
mii.h | 16 #define MII_BMCR 0x00 /* Basic mode control register */
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/external/u-boot/include/linux/ |
mii.h | 13 #define MII_BMCR 0x00 /* Basic mode control register */
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/external/u-boot/drivers/usb/eth/ |
mcs7830.c | 322 rc = mcs7830_write_phy(udev, MII_BMCR, flg); 326 rc = mcs7830_write_phy(udev, MII_BMCR, flg); 330 rc = mcs7830_write_phy(udev, MII_BMCR, flg);
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