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  /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/
invalid-mips32.s 9 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
10 mtc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
11 mfc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
12 mtc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
13 mfc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
  /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips4/
invalid-mips32.s 9 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
10 mtc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
11 mfc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
12 mtc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
13 mfc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
invalid-mips64.s 19 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
22 mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
invalid-mips64r2.s 22 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
26 mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
  /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips5/
invalid-mips32.s 9 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
10 mtc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
11 mfc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
12 mtc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
13 mfc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
invalid-mips64.s 20 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
23 mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
invalid-mips64r2.s 26 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
30 mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
  /build/make/core/combo/arch/mips/
mips32-fp.mk 2 # Generating binaries for MIPS32/hard-float/little-endian
  /external/llvm/test/MC/Mips/
macro-ddiv-bad.s 2 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
4 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
12 # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
macro-ddivu-bad.s 2 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
4 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
12 # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
mips_abi_flags_xx_set.s 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
30 # CHECK-OBJ-NEXT: ISA: {{MIPS32$}}
elf_eflags.s 2 # corresponding options (-mcpu=mips32 -> -mips32 for example).
42 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32 %s
43 # MIPSEL-MIPS32: Flags [ (0x50001004)
45 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32-NAN2008 %s
46 # MIPSEL-MIPS32-NAN2008: Flags [ (0x50001404)
mips_abi_flags_xx.s 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
8 # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=fpxx -filetype=obj -o - | \
41 # CHECK-OBJ-32R1-NEXT: ISA: {{MIPS32$}}
  /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
macro-ddiv-bad.s 2 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
4 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
12 # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
macro-ddivu-bad.s 2 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
4 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
12 # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
macro-seq.s 1 # RUN: llvm-mc -arch=mips -mcpu=mips1 < %s | FileCheck --check-prefixes=ALL,MIPS32 %s
28 # MIPS32: addiu $2, $3, 1546
32 # MIPS32: addiu $2, $2, 7546
51 # MIPS32: move $4, $zero
mips_abi_flags_xx_set.s 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
30 # CHECK-OBJ-NEXT: ISA: {{MIPS32$}}
mips_abi_flags_xx.s 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
8 # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=fpxx -filetype=obj -o - | \
41 # CHECK-OBJ-32R1-NEXT: ISA: {{MIPS32$}}
elf_eflags.s 2 # corresponding options (-mcpu=mips32 -> -mips32 for example).
64 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32 %s
65 # MIPSEL-MIPS32: Flags [ (0x50001004)
67 # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32-NAN2008 %s
68 # MIPSEL-MIPS32-NAN2008: Flags [ (0x50001404)
  /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/
invalid-mips32.s 11 mtc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
12 mfc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
13 mtc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
14 mfc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
  /external/swiftshader/third_party/subzero/src/
IceInstMIPS32.cpp 1 //===- subzero/src/IceInstMips32.cpp - Mips32 instruction implementation --===//
26 namespace MIPS32 {
280 auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
338 Str << "[MIPS32] ";
439 auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
585 auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
610 auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
701 auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
727 auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>();
732 auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>()
    [all...]
IceRegistersMIPS32.h 11 /// \brief Declares the registers and their encodings for MIPS32.
24 namespace MIPS32 {
134 // Extend enum RegClass with MIPS32-specific register classes (if any).
137 } // end of namespace MIPS32
  /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/
invalid-mips32.s 21 mfc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
22 mfc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
42 mtc0 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
43 mtc2 $4, $5, 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
45 sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
invalid-mips32r2.s 61 mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
84 mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: selector must be zero for pre-MIPS32 ISAs
  /external/swiftshader/third_party/subzero/crosstest/
test_calling_conv_main.cpp 72 #ifdef MIPS32

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