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  /device/google/contexthub/firmware/os/platform/stm32/
mpu.c 22 #include <mpu.h>
98 MPU->RNR = regionNo;
99 MPU->RASR = 0; /* disable region before changing it */
100 MPU->RBAR = proposedStart;
101 MPU->RASR = MPU_SRD_BITS | MPU_BIT_ENABLE | attrs | ((lenVal-1) << 1);
122 MPU->CTRL = 0x00; // disable MPU
136 //MPU on, even during faults, supervisor default: allow, user default: default deny
137 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk;
153 int i, regions = (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos
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  /external/u-boot/drivers/power/pmic/
pmic_tps65910.c 35 * tps65910_voltage_update() - Voltage switching for MPU frequency switching.
36 * @module: mpu - 0, core - 1
46 if (module == MPU)
  /external/u-boot/include/power/
tps65910.h 11 #define MPU 0
  /external/u-boot/board/siemens/pxm2/
board.c 83 * voltage switching for MPU frequency switching.
84 * @module = mpu - 0, core - 1
88 #define MPU 0
96 if (module == MPU)
138 * pxm2 PMIC code. All boards currently want an MPU voltage
155 if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
  /external/u-boot/board/vscom/baltos/
board.c 182 * MPU frequencies we support we use a CORE voltage of
183 * 1.1375V. For MPU voltage we need to switch based on
196 * Depending on MPU clock and PG we will need a different
206 /* First update MPU voltage. */
207 if (tps65910_voltage_update(MPU, mpu_vdd))
217 /* Set MPU Frequency to what we detected now that voltages are set */
  /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm0plus.h 221 - Core MPU Register
503 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
504 \brief Type definitions for the Memory Protection Unit (MPU)
508 /** \brief Structure type to access the Memory Protection Unit (MPU).
512 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
513 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
514 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
515 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
516 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
519 /* MPU Type Register *
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core_sc000.h 216 - Core MPU Register
522 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
523 \brief Type definitions for the Memory Protection Unit (MPU)
527 /** \brief Structure type to access the Memory Protection Unit (MPU).
531 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
532 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
533 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
534 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
535 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
538 /* MPU Type Register *
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core_cm3.h 217 - Core MPU Register
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core_cm4.h 263 - Core MPU Register
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core_sc300.h 217 - Core MPU Register
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core_cm7.h 278 - Core MPU Register
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  /external/u-boot/board/ti/am335x/
board.c 383 /* Set DCDC2 (MPU) voltage */
420 * MPU frequencies we support we use a CORE voltage of
421 * 1.10V. For MPU voltage we need to switch based on
428 * Depending on MPU clock and PG we will need a different
437 /* First update MPU voltage. */
438 if (tps65910_voltage_update(MPU, mpu_vdd))

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