| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/ |
| HdLcd.c | 38 MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
41 MmioWrite32(HDLCD_REG_INT_MASK, 0);
44 MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress);
47 MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
48 MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH);
49 MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL);
50 MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));
51 MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));
52 MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));
93 MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
[all...] |
| PL111Lcd.c | 57 MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress);
58 MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer
61 MmioWrite32(PL111_REG_LCD_IMSC, 0);
100 MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1);
103 MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes));
104 MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes));
105 MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes));
106 MmioWrite32 (PL111_REG_LCD_TIMING_3, 0);
110 MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl);
114 MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl);
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV2/ |
| ArmGicV2NonSecLib.c | 30 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
40 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);
41 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);
|
| ArmGicV2SecLib.c | 42 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
60 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
64 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
68 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
78 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
83 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
99 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));
|
| ArmGicV2Lib.c | 35 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D03/EarlyConfigPeim/ |
| EarlyConfigPeimD03.c | 73 MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE);
115 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
116 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
117 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
118 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
119 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
120 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
121 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
123 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
124 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/ |
| OmapDmaLib.c | 70 MmioWrite32 (DMA4_CSDP (Channel), RegVal);
73 MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);
76 MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);
79 MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);
80 MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);
100 MmioWrite32 (DMA4_CCR (Channel), RegVal);
103 MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);
106 MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);
110 MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);
113 MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/Library/DebugAgentTimerLib/ |
| DebugAgentTimerLib.c | 43 MmioWrite32 (INTCPS_ILR (gVector), 1);
48 MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
62 MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
121 MmioWrite32 (gTCLR, TCLR_ST_OFF);
130 MmioWrite32 (gTLDR, LoadValue);
131 MmioWrite32 (gTCRR, LoadValue);
134 MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
137 MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
156 MmioWrite32 (gTISR, TISR_CLEAR_ALL);
161 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D03/Library/OemMiscLib2P/ |
| OemMiscLib2PHi1610.c | 82 MmioWrite32(0xd0002180, 0x3);
83 MmioWrite32(0xd0002194, 0xa4);
84 MmioWrite32(0xd0000a54, 0x1);
88 MmioWrite32(0xd0002108, 0x1);
89 MmioWrite32(0xd0002114, 0x1);
90 MmioWrite32(0xd0002120, 0x1);
91 MmioWrite32(0xd0003108, 0x1);
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/ |
| SasV1Init.c | 48 MmioWrite32(SAS0_BASE + SAS0_RESET, SAS_RESET_VALUE);
49 MmioWrite32(SAS0_BASE + SAS0_DISABLE_CLK, SAS_RESET_VALUE);
53 MmioWrite32(SAS0_BASE + SAS0_DERESET, SAS_RESET_VALUE);
54 MmioWrite32(SAS0_BASE + SAS0_ENABLE_CLK, SAS_RESET_VALUE);
71 MmioWrite32(SAS1_BASE + SAS1_RESET, SAS_RESET_VALUE);
72 MmioWrite32(SAS1_BASE + SAS1_DISABLE_CLK, SAS_RESET_VALUE);
76 MmioWrite32(SAS1_BASE + SAS1_DERESET, SAS_RESET_VALUE);
77 MmioWrite32(SAS1_BASE + SAS1_ENABLE_CLK, SAS_RESET_VALUE);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/ |
| PL180Mci.c | 92 MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);
93 MmioWrite32 (MCI_DATA_LENGTH_REG, MMCI0_BLOCKLEN);
98 MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));
100 MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | MCI_DATACTL_STREAM_TRANS);
124 MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);
125 MmioWrite32 (MCI_DATA_LENGTH_REG, 64);
127 MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | GetPow2BlockLen (64));
129 MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | MCI_DATACTL_STREAM_TRANS);
132 MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF);
134 MmioWrite32 (MCI_DATA_LENGTH_REG, 8);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/ |
| HiKey960UsbDxe.c | 80 MmioWrite32 (
88 MmioWrite32 (USB3OTG_PHY_CR_CTRL, 0);
100 MmioWrite32 (USB3OTG_PHY_CR_CTRL, USB3OTG_PHY_CR_READ);
120 MmioWrite32 (USB3OTG_PHY_CR_CTRL, 0);
134 MmioWrite32 (USB3OTG_PHY_CR_CTRL, Data);
138 MmioWrite32 (USB3OTG_PHY_CR_CTRL, Data);
141 MmioWrite32 (USB3OTG_PHY_CR_CTRL, 0);
142 MmioWrite32 (USB3OTG_PHY_CR_CTRL, USB3OTG_PHY_CR_WRITE);
154 MmioWrite32 (USB3OTG_CTRL4, USB_EYE_PARAM);
169 MmioWrite32 (USB3OTG_CTRL6, Data);
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| PlatformEarlyInit.c | 347 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
348 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
349 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
350 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
351 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
352 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
353 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
354 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
355 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
356 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
[all...] |
| /device/linaro/bootloader/edk2/BeagleBoardPkg/Library/BeagleBoardLib/ |
| Clock.c | 28 MmioWrite32 (CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
29 MmioWrite32 (CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
30 MmioWrite32 (CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/MvMdioDxe/ |
| MvMdioDxe.h | 55 #define MdioRegWrite32(x, y) MmioWrite32((y), (x))
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D02/EarlyConfigPeim/ |
| EarlyConfigPeim.c | 44 MmioWrite32 (TIMER_SUBCTRL_BASE + SC_TM_CLKEN0_REG, 0x3);
78 MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_VALUE);
84 MmioWrite32(PERI_SUB_CTRL_BASE + SYS_APB_IF_BASE + TSENSOR_REG, TSENSOR_CONFIG_VALUE);
85 MmioWrite32(ALG_BASE + SC_HLLC_RESET_DREQ_REG, SC_HLLC_RESET_DREQ_VALUE);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/ArmTrustZone/ |
| ArmTrustZone.c | 44 MmioWrite32 ((UINTN)TzpcBase + TZPC_DECPROT0_SET_REG + (TzpcId * 0x0C), Bits);
63 MmioWrite32 ((UINTN)TzpcBase + TZPC_DECPROT0_CLEAR_REG + (TzpcId * 0x0C), Bits);
101 MmioWrite32((UINTN)(Region), LowAddress&0xFFFF8000);
102 MmioWrite32((UINTN)(Region+1), HighAddress);
103 MmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((Size & 0x3F) << 1) | (Enabled & 0x1));
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/ |
| HiKeyDxe.c | 68 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1);
69 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1);
71 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2);
72 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2);
74 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3);
75 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3);
77 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4);
78 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4);
81 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2);
85 MmioWrite32 (PMUSSI_REG(0x1c), Val)
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Mmc/DwEmmcDxe/ |
| DwEmmcDxe.c | 123 MmioWrite32 (DWEMMC_CMD, Data);
164 MmioWrite32 (DWEMMC_CLKENA, 0);
168 MmioWrite32 (DWEMMC_CLKDIV, Divider);
173 MmioWrite32 (DWEMMC_CLKENA, 1);
174 MmioWrite32 (DWEMMC_CLKSRC, 0);
193 MmioWrite32 (DWEMMC_PWREN, 1);
197 MmioWrite32 (DWEMMC_CTRL, Data);
209 MmioWrite32 (DWEMMC_RINTSTS, ~0);
210 MmioWrite32 (DWEMMC_INTMASK, 0);
211 MmioWrite32 (DWEMMC_TMOUT, ~0);
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/Library/Omap35xxTimerLib/ |
| TimerLib.c | 40 MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
41 MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
44 MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
47 MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
50 MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);
52 MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);
|
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ |
| ArmCortexA9Lib.c | 34 MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
36 MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
|
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/ |
| ArmGicSecLib.c | 41 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
52 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
|
| ArmGicNonSecLib.c | 33 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/ |
| Wtf_Reg.h | 82 MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
90 MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
97 MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
104 MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/ |
| PlatformErratas.c | 132 MmioWrite32 (
139 MmioWrite32 (
147 MmioWrite32 (
154 MmioWrite32 (
|
