| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetLowering.h | 313 unsigned &NumIntermediates,
549 unsigned NumIntermediates;
551 NumIntermediates, RegisterVT);
575 unsigned NumIntermediates;
576 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 857 unsigned &NumIntermediates,
880 NumIntermediates = NumVectorRegs;
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 537 unsigned &NumIntermediates,
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| TargetLowering.h | 714 unsigned &NumIntermediates,
722 unsigned &NumIntermediates, MVT &RegisterVT) const {
723 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 655 unsigned &NumIntermediates,
678 NumIntermediates = NumVectorRegs;
[all...] |
| SelectionDAGBuilder.cpp | 228 unsigned NumIntermediates;
231 NumIntermediates, RegisterVT);
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
249 assert(NumParts % NumIntermediates == 0 &&
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
261 ValueVT, &Ops[0], NumIntermediates);
499 unsigned NumIntermediates;
502 NumIntermediates, RegisterVT)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.h | 38 unsigned &NumIntermediates, MVT &RegisterVT) const override;
|
| SIISelLowering.cpp | 744 unsigned &NumIntermediates, MVT &RegisterVT) const {
752 NumIntermediates = NumElts;
753 return NumIntermediates;
759 NumIntermediates = 2 * NumElts;
760 return NumIntermediates;
769 NumIntermediates = NumElts / 2;
770 return NumIntermediates;
775 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 303 unsigned &NumIntermediates, MVT &RegisterVT) const override;
|
| MipsISelLowering.cpp | 137 unsigned &NumIntermediates, MVT &RegisterVT) const {
141 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
145 return NumIntermediates;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 360 unsigned NumIntermediates;
366 NumIntermediates, RegisterVT);
370 NumIntermediates, RegisterVT);
381 SmallVector<SDValue, 8> Ops(NumIntermediates);
382 if (NumIntermediates == NumParts) {
391 assert(NumParts % NumIntermediates == 0 &&
393 unsigned Factor = NumParts / NumIntermediates;
394 for (unsigned i = 0; i != NumIntermediates; ++i)
405 : NumIntermediates));
687 unsigned NumIntermediates;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 288 unsigned NumIntermediates;
291 NumIntermediates, RegisterVT);
300 SmallVector<SDValue, 8> Ops(NumIntermediates);
301 if (NumIntermediates == NumParts) {
310 assert(NumParts % NumIntermediates == 0 &&
312 unsigned Factor = NumParts / NumIntermediates;
313 for (unsigned i = 0; i != NumIntermediates; ++i)
574 unsigned NumIntermediates;
577 NumIntermediates, RegisterVT);
585 SmallVector<SDValue, 8> Ops(NumIntermediates);
[all...] |
