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    Searched refs:ODPG_WR_RD_MODE_ENA_REG (Results 1 - 5 of 5) sorted by null

/external/u-boot/drivers/ddr/marvell/a38x/
mv_ddr_regs.h	34 #define ODPG_WR_RD_MODE_ENA_REG 0x10fc
ddr3_training_leveling.c	133 ODPG_WR_RD_MODE_ENA_REG, 0, 508 ODPG_WR_RD_MODE_ENA_REG, 0,     [all...]
ddr3_training_pbs.c	875 ODPG_WR_RD_MODE_ENA_REG, 0xffff, MASK_ALL_BITS));
ddr3_training_ip_engine.c	413 ODPG_WR_RD_MODE_ENA_REG, reg_data,     [all...]
ddr3_training.c	[all...]

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