HomeSort by relevance Sort by last modified time
    Searched refs:OPER_WRITE (Results 1 - 5 of 5) sorted by null

  /external/u-boot/drivers/ddr/marvell/a38x/
ddr3_training_bist.c 46 tx_burst_size = (dir == OPER_WRITE) ?
48 delay_between_burst = (dir == OPER_WRITE) ? 2 : 0;
49 rd_mode = (dir == OPER_WRITE) ? 1 : 0;
131 i, OPER_WRITE, STRESS_NONE,
467 if (dir == OPER_WRITE) {
507 mv_ddr_odpg_bist_prepare(pattern, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE,
517 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE,
539 mv_ddr_odpg_bist_prepare(PATTERN_VREF, ACCESS_TYPE_UNICAST, OPER_WRITE, STRESS_NONE, DURATION_SINGLE,
550 ddr3_tip_configure_odpg(0, ACCESS_TYPE_UNICAST, 0, OPER_WRITE,
ddr3_training_ip_def.h 156 OPER_WRITE,
ddr3_training_ip_engine.c 399 tx_burst_size = (direction == OPER_WRITE) ?
401 delay_between_burst = (direction == OPER_WRITE) ? 2 : 0;
402 rd_mode = (direction == OPER_WRITE) ? 1 : 0;
461 direction == OPER_WRITE) {
464 direction == OPER_WRITE) {
479 direction == OPER_WRITE) {
    [all...]
ddr3_training_centralization.c 94 direction = OPER_WRITE;
391 OPER_WRITE) {
ddr3_training_pbs.c 40 enum hws_dir dir = (pbs_mode == PBS_RX_MODE) ? OPER_READ : OPER_WRITE;

Completed in 1033 milliseconds