| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_target_gm107.cpp | 235 case OP_ABS:
271 case OP_ABS:
|
| nv50_ir_lowering_nv50.cpp | 80 bld->mkOp1(OP_ABS, mul->sType, s[0], mul->getSrc(0));
81 bld->mkOp1(OP_ABS, mul->sType, s[1], mul->getSrc(1));
507 bld.mkOp1(OP_ABS, ty, a, div->getSrc(0));
508 bld.mkOp1(OP_ABS, ty, b, div->getSrc(1));
734 src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), i->getSrc(c));
975 src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), crd[c]);
1054 bld.mkOp1(OP_ABS, TYPE_S32, i->getDef(0), i->getDef(0))
[all...] |
| nv50_ir_target_nv50.cpp | 91 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
457 case OP_ABS:
|
| nv50_ir_lowering_gm107.cpp | 156 src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), crd[c]);
|
| nv50_ir_target_nvc0.cpp | 111 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
436 case OP_ABS:
609 case OP_ABS:
|
| nv50_ir_peephole.cpp | 507 case NV50_IR_MOD_ABS: return OP_ABS;
817 case OP_ABS: res.data.f32 = fabsf(imm.reg.data.f32); break;
[all...] |
| nv50_ir_emit_gm107.cpp | 786 emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs());
828 emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs());
870 emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs());
903 emitField(0x31, 1, (insn->op == OP_ABS) || insn->src(0).mod.abs());
[all...] |
| nv50_ir_emit_nv50.cpp | [all...] |
| nv50_ir.h | 61 OP_ABS,
[all...] |
| nv50_ir_emit_gk110.cpp | 1067 case OP_ABS: abs = true; neg = false; break;
[all...] |
| nv50_ir.cpp | 38 case OP_ABS: bits = NV50_IR_MOD_ABS; break;
|
| nv50_ir_emit_nvc0.cpp | 1091 const bool abs = (i->op == OP_ABS) || i->src(0).mod.abs();
1119 if (neg && i->op != OP_ABS)
[all...] |
| nv50_ir_from_tgsi.cpp | [all...] |
| nv50_ir_lowering_nvc0.cpp | 830 src[c] = bld.mkOp1v(OP_ABS, TYPE_F32, bld.getSSA(), i->getSrc(c));
[all...] |
