| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_target_gm107.cpp | 90 if (insn->op == OP_INSBF || insn->op == OP_EXTBF)
209 case OP_INSBF:
|
| nv50_ir_target_nv50.cpp | 437 case OP_INSBF:
|
| nv50_ir_lowering_nvc0.cpp | 903 bld.mkOp3(OP_INSBF, TYPE_U32, hnd, rHnd, bld.mkImm(0x1400), sHnd);
988 bld.mkOp3(OP_INSBF, TYPE_U32, src, ticRel, bld.mkImm(0x0917), src);
990 bld.mkOp3(OP_INSBF, TYPE_U32, src, tscRel, bld.mkImm(0x0710), src);
[all...] |
| nv50_ir.h | 148 OP_INSBF, // insert first src1[8:15] bits of src0 into src2 at src1[0:7]
[all...] |
| nv50_ir_target_nvc0.cpp | 136 { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
|
| nv50_ir_from_tgsi.cpp | [all...] |
| nv50_ir_emit_gk110.cpp | [all...] |
| nv50_ir_emit_nv50.cpp | [all...] |
| nv50_ir_emit_gm107.cpp | [all...] |
| nv50_ir_emit_nvc0.cpp | [all...] |
| nv50_ir_peephole.cpp | 750 case OP_INSBF: {
[all...] |
