| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstrInfo.cpp | 51 int64_t Offset0, int64_t Offset1,
53 assert(Offset1 > Offset0 &&
59 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
|
| SILoadStoreOptimizer.cpp | 15 // ds_read2_b32 v[0:1], v2, offset0:4 offset1:8
65 static bool offsetsCanBeCombined(unsigned Offset0,
130 bool SILoadStoreOptimizer::offsetsCanBeCombined(unsigned Offset0,
135 if (Offset0 == Offset1)
139 if ((Offset0 % Size != 0) || (Offset1 % Size != 0))
142 unsigned EltOffset0 = Offset0 / Size;
181 unsigned Offset0 = I->getOperand(OffsetIdx).getImm() & 0xffff;
185 if (offsetsCanBeCombined(Offset0, Offset1, EltSize))
205 unsigned Offset0
210 unsigned NewOffset0 = Offset0 / EltSize
[all...] |
| AMDGPUISelDAGToDAG.cpp | 90 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
719 SDValue &Offset0,
732 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
758 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
775 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
783 Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
[all...] |
| SIInstrInfo.cpp | 94 int64_t &Offset0,
127 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
151 Offset0 = Load0Offset->getZExtValue();
185 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
223 // The 2 offset instructions use offset0 and offset1 instead. We can treat
227 getNamedOperand(LdSt, AMDGPU::OpName::offset0);
231 uint8_t Offset0 = Offset0Imm->getImm();
234 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
253 Offset = EltSize * Offset0;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SILoadStoreOptimizer.cpp | 15 // ds_read2_b32 v[0:1], v2, offset0:4 offset1:8
92 unsigned Offset0;
250 if (CI.Offset0 == CI.Offset1)
254 if ((CI.Offset0 % CI.EltSize != 0) || (CI.Offset1 % CI.EltSize != 0))
257 unsigned EltOffset0 = CI.Offset0 / CI.EltSize;
275 CI.Offset0 = EltOffset0 / 64;
283 CI.Offset0 = EltOffset0;
290 CI.BaseOff = std::min(CI.Offset0, CI.Offset1);
293 CI.Offset0 = (EltOffset0 - CI.BaseOff / CI.EltSize) / 64;
300 CI.Offset0 = EltOffset0 - CI.BaseOff / CI.EltSize
[all...] |
| SIInstrInfo.cpp | 151 int64_t &Offset0,
184 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
213 Offset0 = Load0Offset->getZExtValue();
247 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
285 // The 2 offset instructions use offset0 and offset1 instead. We can treat
289 getNamedOperand(LdSt, AMDGPU::OpName::offset0);
293 uint8_t Offset0 = Offset0Imm->getImm();
296 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
315 Offset = EltSize * Offset0;
[all...] |
| AMDGPUISelDAGToDAG.cpp | 117 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
[all...] |
| SIInstrInfo.h | 171 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonSubtarget.cpp | 279 int Offset0;
281 unsigned Base0 = HII.getBaseAndOffset(L0, Offset0, Size0);
299 if (((Offset0 ^ Offset1) & 0x18) != 0)
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/ |
| PcieInitLib.c | 56 VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
58 RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
61 UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
64 RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/ |
| PcieInitLib.c | 55 VOID PcieMmioWrite(UINT32 Port, UINTN Offset0, UINTN Offset1, UINT32 Value)
57 RegWrite((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
60 UINT32 PcieMmioRead(UINT32 Port, UINTN Offset0, UINTN Offset1)
63 RegRead((UINT64)mPcieIntCfg.CfgResource[Port] + Offset0 + Offset1, Value);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
