| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 99 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
106 R600::OpName::pred_sel);
108 R600::OpName::pred_sel);
128 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1);
130 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1);
160 TII->getOperandIdx(Opcode, R600::OpName::src0))
163 TII->getOperandIdx(Opcode, R600::OpName::src1))
210 TII->getOperandIdx(MI, R600::OpName::dst)).getReg();
212 TII->getOperandIdx(MI, R600::OpName::src0)).getReg();
217 int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1)
[all...] |
| R600InstrInfo.cpp | 91 NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0))
157 return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1;
258 {R600::OpName::src0, R600::OpName::src0_sel},
259 {R600::OpName::src1, R600::OpName::src1_sel},
260 {R600::OpName::src2, R600::OpName::src2_sel},
261 {R600::OpName::src0_X, R600::OpName::src0_sel_X}
[all...] |
| SIPeepholeSDWA.cpp | 337 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) {
338 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
341 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) {
342 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) {
372 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
373 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel);
375 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
379 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
380 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel);
381 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)
[all...] |
| R600ClauseMergePass.cpp | 88 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT))
95 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled))
101 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT);
120 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT);
132 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0);
134 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0);
136 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0);
148 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1);
150 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1);
152 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR1)
[all...] |
| AMDGPUMacroFusion.cpp | 46 AMDGPU::OpName::src2);
|
| SIShrinkInstructions.cpp | 71 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
86 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
96 TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
105 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
107 TII->hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers)))
112 if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
116 return !TII->hasModifiersSet(MI, AMDGPU::OpName::omod) &&
117 !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp);
127 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
451 TII->getNamedOperand(MI, AMDGPU::OpName::src2)
[all...] |
| SIFoldOperands.cpp | 135 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
169 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0))
170 ModIdx = AMDGPU::OpName::src0_modifiers;
171 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1))
172 ModIdx = AMDGPU::OpName::src1_modifiers;
173 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2))
174 ModIdx = AMDGPU::OpName::src2_modifiers;
234 (int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) {
542 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
546 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0)
[all...] |
| SILoadStoreOptimizer.cpp | 320 AddrOpName[NumAddresses++] = AMDGPU::OpName::addr;
323 AddrOpName[NumAddresses++] = AMDGPU::OpName::sbase;
327 AddrOpName[NumAddresses++] = AMDGPU::OpName::srsrc;
328 AddrOpName[NumAddresses++] = AMDGPU::OpName::vaddr;
329 AddrOpName[NumAddresses++] = AMDGPU::OpName::soffset;
333 AddrOpName[NumAddresses++] = AMDGPU::OpName::srsrc;
334 AddrOpName[NumAddresses++] = AMDGPU::OpName::soffset;
427 AMDGPU::OpName::offset);
436 CI.GLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::glc)->getImm();
437 CI.GLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::glc)->getImm()
[all...] |
| SIInstrInfo.cpp | 110 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
114 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
115 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
180 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
181 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
191 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
192 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
222 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
224 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
225 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)
[all...] |
| R600Packetizer.cpp | 87 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write);
90 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst);
132 R600::OpName::src0,
133 R600::OpName::src1,
134 R600::OpName::src2
188 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel),
189 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel);
223 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last);
304 R600::OpName::bank_swizzle);
308 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle)
[all...] |
| R600ISelLowering.cpp | 302 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
362 int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal);
371 TII->setImmOperand(*NewMI, R600::OpName::src0_sel,
[all...] |
| R600Defines.h | 65 namespace OpName {
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.cpp | 71 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
148 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1;
152 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1;
253 AMDGPU::OpName::src0,
254 AMDGPU::OpName::src1,
255 AMDGPU::OpName::src2
264 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
265 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}
[all...] |
| R600ExpandSpecialInstrs.cpp | 83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
90 AMDGPU::OpName::pred_sel);
92 AMDGPU::OpName::pred_sel);
112 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_exec_mask, 1);
114 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_pred, 1);
223 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
226 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
273 TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg();
275 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
280 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1)
[all...] |
| SIShrinkInstructions.cpp | 84 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
97 TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
106 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
108 TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
115 if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
119 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
122 return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp);
138 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
349 TII->getNamedOperand(MI, AMDGPU::OpName::src2);
369 int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst)
[all...] |
| R600ClauseMergePass.cpp | 77 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT))
84 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::Enabled))
90 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
109 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
121 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0);
123 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0);
125 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0);
137 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1);
139 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK1);
141 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR1)
[all...] |
| SILoadStoreOptimizer.cpp | 171 int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr);
180 AMDGPU::OpName::offset);
200 const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
202 const MachineOperand *Dest0 = TII->getNamedOperand(*I, AMDGPU::OpName::vdst);
203 const MachineOperand *Dest1 = TII->getNamedOperand(*Paired, AMDGPU::OpName::vdst);
206 = TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm() & 0xffff;
208 = TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm() & 0xffff;
295 const MachineOperand *Addr = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
296 const MachineOperand *Data0 = TII->getNamedOperand(*I, AMDGPU::OpName::data0);
298 = TII->getNamedOperand(*Paired, AMDGPU::OpName::data0)
[all...] |
| R600Packetizer.cpp | 89 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
134 AMDGPU::OpName::src0,
135 AMDGPU::OpName::src1,
136 AMDGPU::OpName::src2
190 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
191 OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel);
225 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last);
306 AMDGPU::OpName::bank_swizzle);
310 TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::bank_swizzle)
[all...] |
| SIInstrInfo.cpp | 53 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
57 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
58 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
123 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
124 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
160 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
163 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
166 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
167 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset)
[all...] |
| R600ISelLowering.cpp | 223 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst);
288 int Idx = TII->getOperandIdx(*MIB, AMDGPU::OpName::literal);
296 TII->setImmOperand(*NewMI, AMDGPU::OpName::src0_sel,
[all...] |
| R600Defines.h | 65 namespace OpName {
|
| SIRegisterInfo.cpp | 259 AMDGPU::OpName::vaddr) &&
263 AMDGPU::OpName::offset);
324 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
329 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset);
640 TII->getNamedOperand(*MI, AMDGPU::OpName::src),
641 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
642 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
644 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
655 TII->getNamedOperand(*MI, AMDGPU::OpName::dst),
656 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg()
[all...] |
| /external/tensorflow/tensorflow/core/kernels/ |
| linalg_ops_common.h | 185 #define REGISTER_LINALG_OP_CPU(OpName, OpClass, Scalar) \
187 Name(OpName).Device(DEVICE_CPU).TypeConstraint<Scalar>("T"), OpClass)
189 #define REGISTER_LINALG_OP_GPU(OpName, OpClass, Scalar) \
191 Name(OpName).Device(DEVICE_GPU).TypeConstraint<Scalar>("T"), OpClass)
194 #define REGISTER_LINALG_OP(OpName, OpClass, Scalar) \
195 REGISTER_LINALG_OP_CPU(OpName, OpClass, Scalar)
|
| /external/tensorflow/tensorflow/cc/framework/ |
| scope_internal.h | 56 enum class OpName;
71 Impl(const Scope& other, Tags::OpName, const string& name,
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeGenInstruction.cpp | 159 std::string OpName = Op.substr(1);
163 std::string::size_type DotIdx = OpName.find_first_of(".");
165 SubOpName = OpName.substr(DotIdx+1);
168 OpName = OpName.substr(0, DotIdx);
171 unsigned OpIdx = getOperandNamed(OpName);
271 std::string OpName = P.first;
273 if (OpName.empty()) break;
276 std::pair<unsigned,unsigned> Op = ParseOperandName(OpName, false);
|
