/external/llvm/lib/Target/PowerPC/ |
PPCTLSDynamicCall.cpp | 75 unsigned Opc1, Opc2; 82 Opc1 = PPC::ADDItlsgdL; 86 Opc1 = PPC::ADDItlsldL; 90 Opc1 = PPC::ADDItlsgdL32; 94 Opc1 = PPC::ADDItlsldL32; 105 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
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PPCISelDAGToDAG.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
PPCTLSDynamicCall.cpp | 86 unsigned Opc1, Opc2; 93 Opc1 = PPC::ADDItlsgdL; 97 Opc1 = PPC::ADDItlsldL; 101 Opc1 = PPC::ADDItlsgdL32; 105 Opc1 = PPC::ADDItlsldL32; 121 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
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PPCISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
Mips16ISelLowering.h | 56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2, 60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
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Mips16ISelLowering.cpp | 584 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, 622 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 649 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, 688 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
Mips16ISelLowering.h | 56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2, 60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
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Mips16ISelLowering.cpp | 584 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, 622 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 649 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, 688 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
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/external/swiftshader/third_party/LLVM/include/llvm/Support/ |
PatternMatch.h | 401 template<typename LHS_t, typename RHS_t, unsigned Opc1, unsigned Opc2> 410 if (V->getValueID() == Value::InstructionVal + Opc1 || 416 return (CE->getOpcode() == Opc1 || CE->getOpcode() == Opc2) &&
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/ |
InstCombineVectorOps.cpp | [all...] |
/external/llvm/lib/Target/AMDGPU/ |
SIInstrInfo.cpp | 55 unsigned Opc1 = N1->getMachineOpcode(); 58 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); 100 unsigned Opc1 = Load1->getMachineOpcode(); 103 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) 106 if (isDS(Opc0) && isDS(Opc1)) { 124 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) 132 if (isSMRD(Opc0) && isSMRD(Opc1)) { 157 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { 167 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIInstrInfo.cpp | 112 unsigned Opc1 = N1->getMachineOpcode(); 115 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); 157 unsigned Opc1 = Load1->getMachineOpcode(); 160 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) 163 if (isDS(Opc0) && isDS(Opc1)) { 181 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) 189 if (isSMRD(Opc0) && isSMRD(Opc1)) { 192 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1) 219 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { [all...] |
/external/llvm/include/llvm/IR/ |
PatternMatch.h | 635 template <typename LHS_t, typename RHS_t, unsigned Opc1, unsigned Opc2> 643 if (V->getValueID() == Value::InstructionVal + Opc1 || 649 return (CE->getOpcode() == Opc1 || CE->getOpcode() == Opc2) && [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMCodeEmitter.cpp | [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
X86InstrInfo.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |
X86InstrInfo.cpp | [all...] |
X86IntrinsicsInfo.h | 46 uint16_t Opc1; [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.cpp | [all...] |
X86ISelLowering.cpp | [all...] |
X86IntrinsicsInfo.h | 46 uint16_t Opc1; [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | 375 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; 380 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | 421 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; 426 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) [all...] |
/external/clang/lib/CodeGen/ |
CGBuiltin.cpp | [all...] |