| /external/clang/test/SemaCXX/ |
| PR20705.cpp | 14 class PC {
19 static typename PC<T, Invalid>::Type Foo();
|
| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/MC/ |
| Disassembler.cpp | 33 LLVMDisasmContextRef DCR = LLVMCreateDisasm("x86_64-pc-linux", nullptr, 0,
40 unsigned PC = 0;
42 InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
46 PC += InstSize;
50 InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
54 PC += InstSize;
58 InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
82 unsigned PC = 0;
84 InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
88 PC += InstSize
[all...] |
| /external/u-boot/board/dhelectronics/dh_imx6/ |
| dh_imx6.c | 41 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
45 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
46 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
50 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
51 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
58 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
59 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
63 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
64 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
71 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/PacketRules/ |
| registers_readonly.s | 3 # CHECK: 4:3: error: Cannot write to read-only register `PC'
4 { pc = r0
|
| /external/llvm/unittests/MC/ |
| Disassembler.cpp | 33 LLVMDisasmContextRef DCR = LLVMCreateDisasm("x86_64-pc-linux", nullptr, 0,
40 unsigned PC = 0;
42 InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
46 PC += InstSize;
50 InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
54 PC += InstSize;
58 InstSize = LLVMDisasmInstruction(DCR, BytesP, NumBytes, PC, OutString,
|
| /external/clang/unittests/AST/ |
| CommentParser.cpp | 438 ParagraphComment *PC;
441 ::testing::AssertionResult AR = GetChildAt(C, Idx, PC);
447 ::testing::AssertionResult AR = HasChildCount(PC, 1);
453 ::testing::AssertionResult AR = HasTextAt(PC, 0, Text);
622 ParagraphComment *PC;
623 ASSERT_TRUE(GetChildAt(FC, 0, PC));
625 ASSERT_TRUE(HasChildCount(PC, 2));
626 ASSERT_TRUE(HasTextWithNewlineAt(PC, 0, " Aaa"));
627 ASSERT_TRUE(HasTextAt(PC, 1, " Bbb"));
690 ParagraphComment *PC;
[all...] |
| /external/libcxx/test/std/containers/associative/multimap/multimap.ops/ |
| count.pass.cpp | 145 typedef PrivateConstructor PC;
146 typedef std::multimap<PC, double, std::less<>> M;
150 m.insert ( std::make_pair<PC, double> ( PC::make(5), 1 ));
151 m.insert ( std::make_pair<PC, double> ( PC::make(5), 2 ));
152 m.insert ( std::make_pair<PC, double> ( PC::make(5), 3 ));
153 m.insert ( std::make_pair<PC, double> ( PC::make(7), 1 ))
[all...] |
| find.pass.cpp | 194 typedef PrivateConstructor PC;
195 typedef std::multimap<PC, double, std::less<>> M;
199 m.insert ( std::make_pair<PC, double> ( PC::make(5), 1 ));
200 m.insert ( std::make_pair<PC, double> ( PC::make(5), 2 ));
201 m.insert ( std::make_pair<PC, double> ( PC::make(5), 3 ));
202 m.insert ( std::make_pair<PC, double> ( PC::make(7), 1 ))
[all...] |
| lower_bound.pass.cpp | 205 typedef PrivateConstructor PC;
206 typedef std::multimap<PC, double, std::less<>> M;
210 m.insert ( std::make_pair<PC, double> ( PC::make(5), 1 ));
211 m.insert ( std::make_pair<PC, double> ( PC::make(5), 2 ));
212 m.insert ( std::make_pair<PC, double> ( PC::make(5), 3 ));
213 m.insert ( std::make_pair<PC, double> ( PC::make(7), 1 ))
[all...] |
| upper_bound.pass.cpp | 204 typedef PrivateConstructor PC;
205 typedef std::multimap<PC, double, std::less<>> M;
209 m.insert ( std::make_pair<PC, double> ( PC::make(5), 1 ));
210 m.insert ( std::make_pair<PC, double> ( PC::make(5), 2 ));
211 m.insert ( std::make_pair<PC, double> ( PC::make(5), 3 ));
212 m.insert ( std::make_pair<PC, double> ( PC::make(7), 1 ))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFeatures.h | 79 return Instr->getOperand(2).getReg() != ARM::PC;
80 // ADD PC, SP and BLX PC were always unpredictable,
84 return Instr->getOperand(0).getReg() != ARM::PC;
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(2).getReg() != ARM::PC;
90 return Instr->getOperand(0).getReg() != ARM::PC &&
91 Instr->getOperand(1).getReg() != ARM::PC;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMFeatures.h | 79 return Instr->getOperand(2).getReg() != ARM::PC;
80 // ADD PC, SP and BLX PC were always unpredictable,
84 return Instr->getOperand(0).getReg() != ARM::PC;
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(2).getReg() != ARM::PC;
90 return Instr->getOperand(0).getReg() != ARM::PC &&
91 Instr->getOperand(1).getReg() != ARM::PC;
|
| /external/compiler-rt/lib/esan/ |
| working_set.h | 27 void processRangeAccessWorkingSet(uptr PC, uptr Addr, SIZE_T Size,
|
| /external/llvm/lib/MC/ |
| MCInstrDesc.cpp | 37 unsigned PC = RI.getProgramCounter();
38 if (PC == 0)
40 if (hasDefOfPhysReg(MI, PC, RI))
42 // A variadic instruction may define PC in the variable operand list.
48 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
|
| /external/llvm/test/MC/ARM/ |
| misaligned-blx.s | 23 @ "Align(PC, 4)" during blx operation.
29 blx _misaligned @ PC=0 (mod 4)
31 blx _misaligned @ PC=2 (mod 4)
33 blx _aligned @ PC=0 (mod 4)
35 blx _aligned @ PC=2 (mod 4)
|
| arm-load-store-multiple-deprecated.s | 13 stm sp!, {r0, pc}
14 @ CHECK: warning: use of SP or PC in the list is deprecated
15 @ CHECK: stm sp!, {r0, pc}
18 @ CHECK: warning: use of SP or PC in the list is deprecated
21 stm r1!, {r0, sp, pc}
22 @ CHECK: warning: use of SP or PC in the list is deprecated
23 @ CHECK: stm r1!, {r0, sp, pc}
25 stm r2!, {sp, pc}
26 @ CHECK: warning: use of SP or PC in the list is deprecated
27 @ CHECK: stm r2!, {sp, pc}
[all...] |
| /external/llvm/test/MC/PowerPC/ |
| pr24686.s | 7 # CHECK: LLVM ERROR: Invalid PC-relative half16ds relocation
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| MCInstrDesc.cpp | 37 unsigned PC = RI.getProgramCounter();
38 if (PC == 0)
40 if (hasDefOfPhysReg(MI, PC, RI))
42 // A variadic instruction may define PC in the variable operand list.
48 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| misaligned-blx.s | 23 @ "Align(PC, 4)" during blx operation.
29 blx _misaligned @ PC=0 (mod 4)
31 blx _misaligned @ PC=2 (mod 4)
33 blx _aligned @ PC=0 (mod 4)
35 blx _aligned @ PC=2 (mod 4)
|
| arm-load-store-multiple-deprecated.s | 13 stm sp!, {r0, pc}
14 @ CHECK: warning: use of SP or PC in the list is deprecated
15 @ CHECK: stm sp!, {r0, pc}
18 @ CHECK: warning: use of SP or PC in the list is deprecated
21 stm r1!, {r0, sp, pc}
22 @ CHECK: warning: use of SP or PC in the list is deprecated
23 @ CHECK: stm r1!, {r0, sp, pc}
25 stm r2!, {sp, pc}
26 @ CHECK: warning: use of SP or PC in the list is deprecated
27 @ CHECK: stm r2!, {sp, pc}
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/ |
| registers_readonly.s | 3 # CHECK: 4:1: error: Cannot write to read-only register `PC'
4 pc = r0 define
6 # CHECK: 7:1: error: Cannot write to read-only register `PC'
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| pr24686.s | 7 # CHECK: LLVM ERROR: Invalid PC-relative half16ds relocation
|
| /external/compiler-rt/lib/sanitizer_common/tests/ |
| sanitizer_stacktrace_test.cc | 41 static uptr PC(uptr idx) {
57 fake_stack[i+1] = PC(i + 1); // retaddr
66 start_pc = PC(0);
81 EXPECT_EQ(PC(i*2 - 1), trace.trace[i]);
95 EXPECT_EQ(PC(i*2 - 1), trace.trace[i]);
108 EXPECT_EQ(PC(i*2 - 1), trace.trace[i]);
131 fake_stack[1] = PC(1);
135 EXPECT_EQ(PC(0), trace.trace[0]);
136 EXPECT_EQ(PC(1), trace.trace[1]);
140 // Make one pc a NULL pointer
156 uptr pc = StackTrace::GetCurrentPc(); local
[all...] |
| /external/u-boot/board/ccv/xpress/ |
| xpress.c | 59 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
63 .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
64 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
68 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
69 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
76 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC,
77 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC,
81 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC,
82 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC,
89 .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC,
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm-c/ |
| Disassembler.h | 32 * is at the PC parameter. For some instruction sets, there can be more than
43 typedef int (*LLVMOpInfoCallback)(void *DisInfo, uint64_t PC,
57 * including any PC adjustment, is passed in to the call back in the Value
93 * disassembler for things like adding a comment for a PC plus a constant
98 * instruction is passed indirectly as is the PC of the instruction in
116 /* The input reference is from a PC relative load instruction. */
150 * instruction is at the address specified by the PC parameter. If a valid
157 uint64_t BytesSize, uint64_t PC,
|
