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    Searched refs:PCI_CACHELINE_SIZE_OFFSET (Results 1 - 6 of 6) sorted by null

  /device/linaro/bootloader/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/
PciHostBridgeSupport.c 97 PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET;
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/
PciDevice.c 479 PCI_CACHELINE_SIZE_OFFSET,
  /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/IndustryStandard/
pci22.h 297 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
  /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/
pci22.h 309 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
  /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
Pci22.h 531 #define PCI_CACHELINE_SIZE_OFFSET 0x0C
  /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/
if_msk.c 926 PCI_CACHELINE_SIZE_OFFSET,
938 PCI_CACHELINE_SIZE_OFFSET,
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