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  /external/u-boot/arch/arm/mach-exynos/
dmc_init_ddr3.c 139 val = PHY_CON0_RESET_VAL;
149 val = PHY_CON0_RESET_VAL;
170 val = PHY_CON0_RESET_VAL;
691 writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
692 writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
exynos5_setup.h 254 #define PHY_CON0_RESET_VAL 0x17020a40

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