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/external/u-boot/arch/arm/mach-exynos/ | |
dmc_init_ddr3.c | 144 val = PHY_CON2_RESET_VAL; 164 val = PHY_CON2_RESET_VAL; 697 val = PHY_CON2_RESET_VAL; |
exynos5_setup.h | 265 #define PHY_CON2_RESET_VAL 0x00010004 |