| /external/u-boot/arch/x86/include/asm/arch-braswell/ |
| iomap.h | 12 #define PMC_BASE_ADDRESS 0xfed03000
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/ |
| UartInit.c | 27 #define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address
174 IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
179 MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/ |
| PlatformBaseAddresses.h | 60 #define PMC_BASE_ADDRESS 0xFED03000 // PMC Memory Base Address
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| IchTcoReset.c | 123 *RcrbGcsSaveValue = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG);
124 MmioAnd8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, (UINT8) ~B_PCH_PMC_PM_CFG_NO_REBOOT);
|
| Platform.c | 1044 (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
1046 (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/PlatformCmosLib/ |
| PlatformCmosLib.c | 115 if ((MmioRead8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1) & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) == 0) {
|
| /external/u-boot/arch/x86/include/asm/arch-baytrail/ |
| iomap.h | 34 #define PMC_BASE_ADDRESS 0xfed03000
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| PchInitPeim.c | 146 MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_PWROK_FLR);
154 MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR);
387 if (MmioRead8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1) & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) {
436 PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1 ,
455 IoWrite32 (0xCFC, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
462 MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, BIT24);
532 MmioOr8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, B_PCH_PMC_PM_CFG_NO_REBOOT);
654 PchPlatformPolicyPpi->PmcBase = PMC_BASE_ADDRESS;
|
| BootMode.c | 354 GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);
|
| PlatformEarlyInit.c | 666 GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);
683 MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/MonoStatusCode/ |
| PlatformStatusCode.c | 342 IoWrite32 (PCI_DAT, (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));
347 MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformSmm/ |
| Platform.c | 509 PmCon1 = MmioRead8 ( PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1 );
514 MmioWrite8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, PmCon1);
|
| /external/u-boot/arch/x86/include/asm/arch-baytrail/acpi/ |
| southcluster.asl | 171 Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformPei/ |
| BootMode.c | 282 GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);
|
| Platform.c | 475 DataUint16 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);
584 (UINT32)((PMC_BASE_ADDRESS & B_PCH_LPC_PMC_BASE_BAR) | B_PCH_LPC_PMC_BASE_EN)
[all...] |
| /external/u-boot/arch/x86/cpu/baytrail/ |
| acpi.c | 167 * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses
185 gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/ |
| MiscOemType0x94Function.c | 789 Data8 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PRSTS)>>16)&0x00FF);
790 Data8_1 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PRSTS)>>24)&0x00FF);
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformSetupDxe/ |
| SetupInfoRecords.c | [all...] |
