1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010,2011 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7 #ifndef _TEGRA20_PINMUX_H_ 8 #define _TEGRA20_PINMUX_H_ 9 10 /* 11 * Pin groups which we adjust. There are three basic attributes of each pin 12 * group which use this enum: 13 * 14 * - function 15 * - pullup / pulldown 16 * - tristate or normal 17 */ 18 enum pmux_pingrp { 19 /* APB_MISC_PP_TRISTATE_REG_A_0 */ 20 PMUX_PINGRP_ATA, 21 PMUX_PINGRP_ATB, 22 PMUX_PINGRP_ATC, 23 PMUX_PINGRP_ATD, 24 PMUX_PINGRP_CDEV1, 25 PMUX_PINGRP_CDEV2, 26 PMUX_PINGRP_CSUS, 27 PMUX_PINGRP_DAP1, 28 29 PMUX_PINGRP_DAP2, 30 PMUX_PINGRP_DAP3, 31 PMUX_PINGRP_DAP4, 32 PMUX_PINGRP_DTA, 33 PMUX_PINGRP_DTB, 34 PMUX_PINGRP_DTC, 35 PMUX_PINGRP_DTD, 36 PMUX_PINGRP_DTE, 37 38 PMUX_PINGRP_GPU, 39 PMUX_PINGRP_GPV, 40 PMUX_PINGRP_I2CP, 41 PMUX_PINGRP_IRTX, 42 PMUX_PINGRP_IRRX, 43 PMUX_PINGRP_KBCB, 44 PMUX_PINGRP_KBCA, 45 PMUX_PINGRP_PMC, 46 47 PMUX_PINGRP_PTA, 48 PMUX_PINGRP_RM, 49 PMUX_PINGRP_KBCE, 50 PMUX_PINGRP_KBCF, 51 PMUX_PINGRP_GMA, 52 PMUX_PINGRP_GMC, 53 PMUX_PINGRP_SDIO1, 54 PMUX_PINGRP_OWC, 55 56 /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ 57 PMUX_PINGRP_GME, 58 PMUX_PINGRP_SDC, 59 PMUX_PINGRP_SDD, 60 PMUX_PINGRP_RESERVED0, 61 PMUX_PINGRP_SLXA, 62 PMUX_PINGRP_SLXC, 63 PMUX_PINGRP_SLXD, 64 PMUX_PINGRP_SLXK, 65 66 PMUX_PINGRP_SPDI, 67 PMUX_PINGRP_SPDO, 68 PMUX_PINGRP_SPIA, 69 PMUX_PINGRP_SPIB, 70 PMUX_PINGRP_SPIC, 71 PMUX_PINGRP_SPID, 72 PMUX_PINGRP_SPIE, 73 PMUX_PINGRP_SPIF, 74 75 PMUX_PINGRP_SPIG, 76 PMUX_PINGRP_SPIH, 77 PMUX_PINGRP_UAA, 78 PMUX_PINGRP_UAB, 79 PMUX_PINGRP_UAC, 80 PMUX_PINGRP_UAD, 81 PMUX_PINGRP_UCA, 82 PMUX_PINGRP_UCB, 83 84 PMUX_PINGRP_RESERVED1, 85 PMUX_PINGRP_ATE, 86 PMUX_PINGRP_KBCC, 87 PMUX_PINGRP_RESERVED2, 88 PMUX_PINGRP_RESERVED3, 89 PMUX_PINGRP_GMB, 90 PMUX_PINGRP_GMD, 91 PMUX_PINGRP_DDC, 92 93 /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ 94 PMUX_PINGRP_LD0, 95 PMUX_PINGRP_LD1, 96 PMUX_PINGRP_LD2, 97 PMUX_PINGRP_LD3, 98 PMUX_PINGRP_LD4, 99 PMUX_PINGRP_LD5, 100 PMUX_PINGRP_LD6, 101 PMUX_PINGRP_LD7, 102 103 PMUX_PINGRP_LD8, 104 PMUX_PINGRP_LD9, 105 PMUX_PINGRP_LD10, 106 PMUX_PINGRP_LD11, 107 PMUX_PINGRP_LD12, 108 PMUX_PINGRP_LD13, 109 PMUX_PINGRP_LD14, 110 PMUX_PINGRP_LD15, 111 112 PMUX_PINGRP_LD16, 113 PMUX_PINGRP_LD17, 114 PMUX_PINGRP_LHP0, 115 PMUX_PINGRP_LHP1, 116 PMUX_PINGRP_LHP2, 117 PMUX_PINGRP_LVP0, 118 PMUX_PINGRP_LVP1, 119 PMUX_PINGRP_HDINT, 120 121 PMUX_PINGRP_LM0, 122 PMUX_PINGRP_LM1, 123 PMUX_PINGRP_LVS, 124 PMUX_PINGRP_LSC0, 125 PMUX_PINGRP_LSC1, 126 PMUX_PINGRP_LSCK, 127 PMUX_PINGRP_LDC, 128 PMUX_PINGRP_LCSN, 129 130 /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ 131 PMUX_PINGRP_LSPI, 132 PMUX_PINGRP_LSDA, 133 PMUX_PINGRP_LSDI, 134 PMUX_PINGRP_LPW0, 135 PMUX_PINGRP_LPW1, 136 PMUX_PINGRP_LPW2, 137 PMUX_PINGRP_LDI, 138 PMUX_PINGRP_LHS, 139 140 PMUX_PINGRP_LPP, 141 PMUX_PINGRP_RESERVED4, 142 PMUX_PINGRP_KBCD, 143 PMUX_PINGRP_GPU7, 144 PMUX_PINGRP_DTF, 145 PMUX_PINGRP_UDA, 146 PMUX_PINGRP_CRTP, 147 PMUX_PINGRP_SDB, 148 149 /* these pin groups only have pullup and pull down control */ 150 PMUX_PINGRP_CK32, 151 PMUX_PINGRP_DDRC, 152 PMUX_PINGRP_PMCA, 153 PMUX_PINGRP_PMCB, 154 PMUX_PINGRP_PMCC, 155 PMUX_PINGRP_PMCD, 156 PMUX_PINGRP_PMCE, 157 PMUX_PINGRP_XM2C, 158 PMUX_PINGRP_XM2D, 159 PMUX_PINGRP_COUNT, 160 }; 161 162 /* 163 * Functions which can be assigned to each of the pin groups. The values here 164 * bear no relation to the values programmed into pinmux registers and are 165 * purely a convenience. The translation is done through a table search. 166 */ 167 enum pmux_func { 168 PMUX_FUNC_DEFAULT, 169 PMUX_FUNC_AHB_CLK, 170 PMUX_FUNC_APB_CLK, 171 PMUX_FUNC_AUDIO_SYNC, 172 PMUX_FUNC_CRT, 173 PMUX_FUNC_DAP1, 174 PMUX_FUNC_DAP2, 175 PMUX_FUNC_DAP3, 176 PMUX_FUNC_DAP4, 177 PMUX_FUNC_DAP5, 178 PMUX_FUNC_DISPA, 179 PMUX_FUNC_DISPB, 180 PMUX_FUNC_EMC_TEST0_DLL, 181 PMUX_FUNC_EMC_TEST1_DLL, 182 PMUX_FUNC_GMI, 183 PMUX_FUNC_GMI_INT, 184 PMUX_FUNC_HDMI, 185 PMUX_FUNC_I2C, 186 PMUX_FUNC_I2C2, 187 PMUX_FUNC_I2C3, 188 PMUX_FUNC_IDE, 189 PMUX_FUNC_KBC, 190 PMUX_FUNC_MIO, 191 PMUX_FUNC_MIPI_HS, 192 PMUX_FUNC_NAND, 193 PMUX_FUNC_OSC, 194 PMUX_FUNC_OWR, 195 PMUX_FUNC_PCIE, 196 PMUX_FUNC_PLLA_OUT, 197 PMUX_FUNC_PLLC_OUT1, 198 PMUX_FUNC_PLLM_OUT1, 199 PMUX_FUNC_PLLP_OUT2, 200 PMUX_FUNC_PLLP_OUT3, 201 PMUX_FUNC_PLLP_OUT4, 202 PMUX_FUNC_PWM, 203 PMUX_FUNC_PWR_INTR, 204 PMUX_FUNC_PWR_ON, 205 PMUX_FUNC_RTCK, 206 PMUX_FUNC_SDIO1, 207 PMUX_FUNC_SDIO2, 208 PMUX_FUNC_SDIO3, 209 PMUX_FUNC_SDIO4, 210 PMUX_FUNC_SFLASH, 211 PMUX_FUNC_SPDIF, 212 PMUX_FUNC_SPI1, 213 PMUX_FUNC_SPI2, 214 PMUX_FUNC_SPI2_ALT, 215 PMUX_FUNC_SPI3, 216 PMUX_FUNC_SPI4, 217 PMUX_FUNC_TRACE, 218 PMUX_FUNC_TWC, 219 PMUX_FUNC_UARTA, 220 PMUX_FUNC_UARTB, 221 PMUX_FUNC_UARTC, 222 PMUX_FUNC_UARTD, 223 PMUX_FUNC_UARTE, 224 PMUX_FUNC_ULPI, 225 PMUX_FUNC_VI, 226 PMUX_FUNC_VI_SENSOR_CLK, 227 PMUX_FUNC_XIO, 228 PMUX_FUNC_RSVD1, 229 PMUX_FUNC_RSVD2, 230 PMUX_FUNC_RSVD3, 231 PMUX_FUNC_RSVD4, 232 PMUX_FUNC_COUNT, 233 }; 234 235 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 236 #include <asm/arch-tegra/pinmux.h> 237 238 #endif /* _TEGRA20_PINMUX_H_ */ 239
